grlib_tester / logic_top

UHCL-CENG-SeniorProject-2021 / FPGA

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Closed bklolo closed 3 years ago

bklolo commented 3 years ago

grlib_tester is logic_top with a different name.

A rename/replacement can be pushed to master branch.

UHCL-CENG-SeniorProject-2021 commented 3 years ago

Deleted grlib_tester 9a5d006 Edited logic_top to reflect deletion a858d8a

bklolo commented 3 years ago

closing issue