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UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
https://uvvm.github.io/
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Modelsim 2019.2 and UVVM Simple #128

Closed bdecelles closed 3 years ago

bdecelles commented 3 years ago

My group seems to be moving to Modelsim 2019.2 from Modelsim DE 10.6 due to moving to Vivado 2019.2. I see the note on UVVM about issues with Modelsim 2019.2. Can someone tell me what the issues are and if I will face any Modelsim crashes if I am using just the UVVM BFMs and UVVM uvvm_util compiled Lib? I can move this question to the GitHub forum or another.

mariuselv commented 3 years ago

Hi, if I remember correctly there was an issue with Modelsim 2019.2 and some of the VVCs. If you run in to some problems you could try with UVVM Light, a published version of UVVM without VVCs.

Br, Marius

bdecelles commented 3 years ago

Hi Thanks for the reply. We might be OK. We are essentially using UVVM light and taking the BFMs and creating our own Generators. The gens are real simple but work well for our needs. We have about 15 additional interface protocols built up with gen and bfm mostly proprietary. Thanks for the roadmap and details.

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On Jan 14, 2021, at 4:29 AM, mariuselv notifications@github.com wrote:

 Hi, if I remember correctly there was an issue with Modelsim 2019.2 and some of the VVCs. If you run in to some problems you could try with UVVM Light, a published version of UVVM without VVCs.

Br, Marius

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