[Bug] vvc_generator generates uncompilable code

UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/

Apache License 2.0

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Hi,

when using the vvc_generator to generate a basic VVC without channels and transaction info, the created code includes some errors.

In order to solve the compile issues you need to:

Add AWAIT_COMPLETION and AWAIT_ANY_COMPLETION to t_operation in vvc_cmd_pkg.vhd
Change the type of command_queue and result_queue to work.td_cmd_queue_pkg.t_generic_queue in the main _vvc.vhd
Change the call for initialization of the interpreter to work.td_vvc_entity_support_pkg.initialize_interpreter(terminate_current_cmd, global_awaiting_completion); in in the main _vvc.vhd

kind regards Thiemo

UVVM / UVVM

[Bug] vvc_generator generates uncompilable code #206