UVVM / UVVM

UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
https://uvvm.github.io/
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Compile script reference to sim #41

Closed eschmidscs closed 6 years ago

eschmidscs commented 6 years ago

Hej

I'm not sure what the intention is: The compile tcl-scripts reference the sim directory for each part. This directory however is not in the repo in all cases. I "fixed" that in some scripts by replacing "sim" with "scripts" (see scriptpath-branch in my fork). But maybe you would prefer to have the sim-directory everywhere?

BR/emanuel

eschmidscs commented 6 years ago

Sorry, that was pretty incomplete...

The reason seems the sim directory that exists for uvvm_util and uvvm_vvc_framework, but not for bitvis_vip_axistream. So either this directory should exist or the script should reference another path (like script).

UVVM commented 6 years ago

Hi Emanuel, Thank you for your feedback. This error will be fixed in the next release.

Best regards, Marius