Checklist

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www.aqdi.com/wordpress/PCBChecklistLive.htm

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A. Electronic and Schematics

• [x] all unused inputs terminated
• [x] race conditions checked
• [x] Darlington outputs (1.2v low) driving logic inputs
• [x] mating connectors on different assemblies checked for same pinout
• [x] all outside world I/O lines filtered for RFI
• [x] all outside world I/O lines protected against static discharge
• [x] bypass cap for each IC
• [x] voltage ratings of components checked — as was not done in the on-board computer in my 1990 Geo Tracker, apparently manufactured by Mitsubishi, where capacitor C4 was rated at 47uf/50V across an automotive rail which can easily see larger spikes. Other owners reported such problems in vehicles from 1990 to 1995, with the capacitor spewing electrolyte onto the conformally coated PCB, corroding conductors in the vicinity. Hats off to Mitsubishi for ignoring a simple checklist item for five years and who knows how many hundred thousand vehicle shipments, and who knows how many in-service failures.
• [x] each IC has predictable or controlled power-up state
• [x] file name on each sheet
• [x] dot on each connection
• [x] minimum number of characters in values
• [x] consistent character size for readability
• [x] schematics printed at a readable scale
• [x] all components have reference designators and values
• [x] special PCB or parts list information entered for each component, if required
• [x] polarized components checked
• [x] electrolytic and tantalum capacitors checked for no reverse voltage
• [x] power and ground pins listed for each component with hidden power pins
• [x] check hidden power and ground connections
• [x] title block completed for each sheet
• [x] ground made first and breaks last for hot pluggability
• [x] pullups on all open collector outputs
• [x] sufficient power rails for analog circuits
• [x] LM324 and LM358 outputs loaded to prevent crossover distortion
• [x] amplifiers checked for stability
• [x] oscillators checked for reliable startup
• [x] consider signal rate-of-rise and fall for noise radiation
• [x] check for input voltages applied with power off and CMOS latchup possibilities
• [x] reset circuit design reliable, both glitch-free and consistent; tested with slow power supply fall time
• [x] separate analog signals from noisy or digital signals
• [x] ability to disable watchdog timer for testing and diagnostics and emulation
• [x] sufficient capacitance on low dropout voltage regulators
• [x] setup, hold, access times for data and address busses
• [x] check the data sheet fine print and apnotes for weird IC behaviors
• [x] determine effect of losing each of multiple grounds on a connector
• [x] automotive powered devices must withstand 60 to 100 volt surges
• [x] check maximum power dissipation at worst-case operating temperatures
• [x] check time delays and slew rates of opamps used as comparators
• [x] check opamp input over-drive response for unintended output inversion
• [x] check common mode input voltages on opamps
• [x] check for voltage transients and high voltages on FET gates
• [x] check failure modes and effects of failed power semiconductors
• [x] estimate total worst case power supply current
• [x] check pin numbers of all custom-generated parts
• [x] for buses, ensure bus order matches device order
• [x] ensure resistors are operating within their specified power range plus safety factor
• [x] resistor power ratings derated for elevated ambient temperatures
• [x] electrolytic/tantalum capacitor temperature/voltage derating sufficient for MTBF
• [x] check for low impedance sources driving tantalum caps which can cause premature failure
• [x] avoid reverse base-emitter current/voltage on bipolar transistors
• [x] use of baud rate friendly clock source for devices that have serial ports
• [x] ~IOR and ~IOW strobes on UARTs are typically incompatible with timings of signals readily available on many processors
• [x] ROHS compliance requirement review
• [x] part obsolescence review
• [x] replacement part compatibility with software requirements: “top-boot vs. bottom boot FLASH”, UART compatibility, SPI memory timing and addressing for different sized parts
• [x] all PCB signal changes noted to the software geeks
• [x] all no-connect pins on IC’s should be labelled NC
• [x] text should not overlap wire or symbol graphics on schematics
• [x] busses with off-page destinations present with title at page margin
• [x] card edge connectors identify mating part
• [x] page title present and consistent on all pages if not in title block
• [x] under-utilization of gates on multi-gate parts checked
• [x] off board connectors identify all signals even if not used on this design
• [x] unpopulated parts annotated and enclosed by dashed-line box on schematics
• [x] wires exist between all connected pins/ports (no direct pin/pin connections) if capture package does not like such connections
• [x] symbols identify open collector/drain pins and internal pulled up/down pins
• [x] clock lines with series termination and parallel termination component locations present even if not populated; zero ohm resistor for series, unpopulated parts for parallel termination
• [x] avoid direct connect of mode pins or no-connect bus lines to GND or VCC so PCB rework options are maximal
• [x] diagnostic resources by design (leds, serial ports, etc.) even if unpopulated by default
• [x] pin names and attributes on symbols with multi-function pins should match actual design usage (I/O/Bi, Name)
• [x] connect DIP switches and other grouped I/O to ports in a logical way, LS bit to LS bit, MS bit to MS bit
• [x] piezo elements generate voltages (when shocked) that can destroy their drivers — check for susceptibility
• [x] preferred component reference designators
  • [x] R fixed resistor
  • [x] RN resistor network
  • [x] RV variable resistor
  • [x] C capacitor (network, fixed or variable)
  • [x] L inductor
  • [x] Q transistor, FET, SCR, TRIAC
  • [x] D,CR diode, rectifier, Zener, varicap, LED
  • [x] DL multisegment display (any type)
  • [x] VR,Q,IC voltage regulator
  • [x] U,IC integrated circuit
  • [x] J socket, jack (female)
  • [x] P plug (male)
  • [x] JP jumper (pins, trace, or wire)
  • [x] Y,X crystal
  • [x] M modular subassembly, daughter board
  • [x] S mechanical switch
  • [x] F fuse
  • [x] FL filter
  • [x] T transformer
  • [x] KB keyboard
  • [x] B,BT battery

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B. PCB Design

• [x] hole diameter on drawing are finished sizes, after plating.
• [x] finished hole sizes are >=10 mils larger than lead
• [x] silkscreen legend text weight >=10 mils
• [x] pads >=15 mils larger than finished hole sizes
• [x] place thruhole components on 50 mil grid
• [x] no silkscreen legend text over vias (if vias not soldermasked) or holes
• [x] soldermask does or does not cover vias
• [x] all legend text reads in one or two directions
• [x] components labeled left-right, top-bottom
• [x] company logo in silkscreen legend
• [x] company logo in foil
• [x] copyright notice on PCB
• [x] date code on PCB
• [x] PCB part number
• [x] assembly part number on PCB
• [x] all polarized components point same way
• [x] components >=0.2″ from edge of PCB
• [x] ground planes where possible
• [x] test pad or test via on every net to allow in circuit test
• [x] test pads 200 mils from edge of board
• [x] mounting holes electrically isolated or not
• [x] mounting holes with or without islands
• [x] proper mounting hole clearance for hardware
• [x] all polarized components checked
• [x] no acute inside angles in foil
• [x] traces >= 20 mils from edge of PCB
• [x] PCB revision on silkscreen legend
• [x] assembly revision blank on silkscreen legend
• [x] serial number blank on silkscreen legend
• [x] soldermask swell checked
• [x] thru hole drill tolerance noted
• [x] thru hole soldermask tolerance noted
• [x] thru hole route tolerance noted
• [x] thru hole silkscreen legend tolerance noted
• [x] drill legend shows all symbols and sizes
• [x] mounting holes matched 1:1 with mating parts
• [x] automated netlist check
• [x] manual netlist check
• [x] check netlist for nodes with only one connection
• [x] CAD design rule check
• [x] drill origin is a tooling hole
• [x] checkplots sent with disk based photoplot files
• [x] NC drill and photoplot file language format noted
• [x] tools on drill plot and NC drill file cross checked
• [x] soldermask over bare copper noted if needed
• [x] PCB thickness, material, copper weight noted
• [x] trace and space geometry noted
• [x] printed drill report sent with checkplots
• [x] printed aperture table sent with checkplots
• [x] photoplot files checked in file viewer
• [x] test coupon on PCB containing minimum geometry features
• [x] trace width sufficient for current carried
• [x] minimum component body spacing
• [x] SMD pad shapes checked
• [x] visual references for automated assembly
• [x] tooling holes for automated assembly
• [x] sufficient clearance for high voltage traces
• [x] component and trace keepout areas observed
• [x] high frequency circuitry precautions observed
• [x] thermal reliefs for internal power layers
• [x] solder paste mask openings are proper size
• [x] blind and buried vias allowed on multilayer PCB
• [x] PCB layout panelized correctly
• [x] panelized PCB fits test and manufacturing equipment
• [x] sufficient clearance for socketed ICs
• [x] SMD component orientation arbitrary or consistent
• [x] ensure pin 1 interpretation and orientation consistent among all connectors of a given type on the board
• [x] clearance for IC extraction tools
• [x] clearance for emulator adapter or pod
• [x] clearance for sockets for ICs during proto phase
• [x] standoffs on power resistors or other hot components
• [x] digital and analog signal commons joined at only one point
• [x] EMI and RFI filtering as close as possible to exit and entry points in shielded areas
• [x] layout PCB so that any rework or repair of a component does not require removal of other components
• [x] extra connector and IC pins accessible on prototype boards, just in case
• [x] check all power and ground connections to ICs
• [x] provide ground test points, accessible and sized for scope ground clip
• [x] potentiometers should increase controlled quantity clockwise
• [x] check hole diameters for odd components: rectangular pins, spring pins
• [x] check the orientation of all connectors using actual connector/cable
• [x] bypass capacitors located close to IC power pins
• [x] all silkscreen text located to be readable when the board is populated
• [x] all ICs have pin one clearly marked, visible even when chip is installed
• [x] high pin count ICs and connectors have corner pins numbered for ease of location
• [x] silk screen tick marks for every 5th or 10th pin on high pin count ICs and connectors
• [x] verify that all series terminators are located near the source
• [x] place I/O drivers near where their signals leave the board
• [x] high frequency crystal cases should be flush to the PCB and grounded
• [x] check for traces running under noisy or sensitive components
• [x] check IC pin count on layout vs schematic
• [x] no vias under metal-film resistors and similar poorly insulated parts
• [x] check for traces which may be susceptible to solder bridging
• [x] maximize distances between features where possible
• [x] check for dead-end traces
• [x] check for power not shorted to ground
• [x] ensure schematic software did / did not separate Vcc from Vdd, Vss from GND as needed
• [x] provide multiple vias for high current and/or low impedance traces
• [x] coupons for board part number, anti-static warning, QC markings
• [x] PCB has ground turrets, power rail test points, and test points for for important signals, all labeled

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C. PCB Assemblies

• [ ] miscellaneous parts on bill of materials and assembly notes for same: hardware, heat sinks, heat sink compound or composite insulators, IC sockets, consumables
• [ ] assembly notes for all special operations
• [ ] conformal coating
• [ ] special static handling precautions required during assembly and test

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D. Wired Assemblies

• [ ] wire gauge checked for compatibility with each termination
• [ ] cable ties or lacing cord shown where needed
• [ ] length &color of each wire indicated
• [ ] notes about application of wire terminations (technique, heat shrink tubing, amount of solder, crimp force, tools, etc.)

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E. Parts Lists

• [ ] each component has quantity, reference designator and description
• [ ] list qualified part numbers for special devices
• [ ] suggested and alternate manufacturer(s) listed
• [ ] object/binary code and method/programmer specified for each programmable device
• [ ] price and availability checked for each component

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F. Mechanical Drawings

• [ ] standard title block and border used
• [ ] no dimensions on the material
• [ ] every feature must have X and Y dimension, along with radius, diameter, etc.
• [ ] every hole must be checked for alignment with mating hole(s) in other parts
• [ ] check every hole diameter
• [ ] tolerance for sheet metal feature position noted
• [ ] tolerance for sheet metal hole size noted
• [ ] specify material
• [ ] specify finish
• [ ] specify units
• [ ] specify debur or brush
• [ ] details for special operations
• [ ] file name on each sheet
• [ ] CAD layers shown on drawing
• [ ] all hardware specified and listed on parts list
• [ ] screw lengths checked; extra thread required for fasteners (nut, lockwasher, washer)
• [ ] hole diameters checked for each screw
• [ ] tapped hole thread details indicated

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G. Software

• [ ] each version archived for future reference
• [ ] loops checked for terminating conditions
• [ ] communications timeouts checked
• [ ] all branches tested
• [ ] revision history noted for all changes
• [ ] CPU utilization measured
• [ ] interrupt response time measured
• [ ] interrupt execution time measured
• [ ] naming conventions consistent and relevant to humans
• [ ] adherence to coding style standards
• [ ] power-up, power-down considerations
• [ ] unused vectors trapped to restart or damage control routine
• [ ] unused ROM space loaded with trap or restart instructions
• [ ] warm and cold reset differences
• [ ] nonvolatile memory corruption possibilities checked during power-up, power-down, and program-gone-wild conditions
• [ ] design notes within or separate from code
• [ ] check for FIFO and buffer overruns
• [ ] check critical timer driver code
• [ ] check for odd address usage on 16/32 bit micros, especially an odd stack pointer
• [ ] use a LINT utility on C programs to find subtle problems
• [ ] program’s data structures contain version numbers to detect program version upgrades and translate the structures’ formats

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H. Testability

• [ ] test points on PCBs for critical circuits, hard to reach nets
• [ ] test pads for in-circuit or bed-of-nails functional testing
• [ ] test pads on a regular grid
• [ ] test procedure written for each test phase
• [ ] special test arrangements and connectors for testing

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I. Maintainability

• [ ] easy disassembly and reassembly
• [ ] fuses accessible and labeled
• [ ] self test mode
• [ ] spare parts available
• [ ] status LEDs on PCB
• [ ] event logging of exceptional conditions
• [ ] vibration tolerance of entire assembly and individual modules
• [ ] surge current magnitude through semiconductors within rating
• [ ] thermal cycling excursions internal to components and assemblies within acceptable limits
• [ ] capacitors mounted below or away from heat-dissipating devices such as transformers
• [ ] resistance and tolerance of entire product to static discharge via any path

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J. Safety

• [ ] fuse and circuit breaker size and characteristics
• [ ] fuse sizes marked near fuse holder
• [ ] room to remove fuse without damaging other components
• [ ] spare fuse storage
• [ ] shock hazards
• [ ] radiated energy warnings and shields
• [ ] applicable standards checked
• [ ] protection against liquids and foreign objects

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K. Documentation

• [ ] end-user instructions: unpacking, how to use, warranty, service, troubleshooting
• [ ] service manual: troubleshooting procedures, parts lists, helpline info
• [ ] design notes: why significant design decisions were made the way they were
• [ ] other info that may be lost if designers depart the organization