[AArch64] Check all floating point convert instruction execution logic

[FinnWilkinson]

Akin to issue #365 , all floating point convert instructions should be double checked to a) ensure the execution logic is correct (i.e. using signed or unsigned types correctly), and b) add checks for ±nan and ±inf.

To do this, the ISA specification should be consulted along with custom c/c++/ (via insline asm) or assembly kernels to validate the results on hardware; then using these results to help write regression tests.

Instructions to check:

• [ ] FCVTAS
• [ ] FCVT
• [ ] FCVTL
• [ ] FCVTL2
• [ ] FCVTN
• [ ] FCVTN2
• [ ] FCVTZS
• [ ] SCVTF
• [ ] UCVTF

[jj16791]

Need to ensure we also account for the cases where the input value has a width greater than the destination register. In this case, it should be set to the max value of the destination register value.

An example taken from Arm Architecture Reference Manual for A-profile architecture:J1.3 Shared pseudocode:shared/functions/vector/UnsignedSatQ which is applicable for the fcvtzu instructions:

if i > 2^N - 1 then
    result = 2^N - 1; saturated = TRUE;
elsif i < 0 then
    result = 0; saturated = TRUE;
else
    result = i; saturated = FALSE;

It may be worth double checking this functionality on the XCI nodes/A64FX nodes/Local Apple Silicon