This PR updates SimEng to work with a newer release of Capstone who's AArch64 engine is based on LLVM18, hence allowing SME2 support.
The reccommended version of LLVM has also been changed to 18.1.8 and the test suite has been updated to work with this version in order to dissassemble new AArch64 instructions.
Closes Issue #349
There have been large changes to Capstone internally for AArch64, some of the main ones which effect our current development / usage include:
A writeback from a pre/post index load/store is now included as an implicit destination. Hence, in instruction_execute the updated base address register is resuts[0] rather than results[1] (for example).
Post index immediate operands are now included as part of the memory operand in mem.disp. Post indexing with a register however is added as an additional operand.
Aliasing can be dissabled for auto-sync architectures, and has been done for AArch64. This means expected registers for the operand are now correct and allows us to remove revertalias() from instruction_metadata completely! The only oddity is the mnemonic and operandStr are still that of the alias. This means exceptions or debugging print statements may be confusing. To indicate aliases better, an isAlias bool has been added to the metadata and exception print out.
[x] Get automatic LLVM download and install working for version 18.1.8
[x] Add AArch64 multi-vector operand enum decoding logic to instruction_decode
No longer required as multi-vector operands already give each register individually rather than using the multi-register enums
This PR updates SimEng to work with a newer release of Capstone who's AArch64 engine is based on LLVM18, hence allowing SME2 support.
The reccommended version of LLVM has also been changed to 18.1.8 and the test suite has been updated to work with this version in order to dissassemble new AArch64 instructions.
Closes Issue #349
There have been large changes to Capstone internally for AArch64, some of the main ones which effect our current development / usage include:
A writeback from a pre/post index load/store is now included as an implicit destination. Hence, in instruction_execute the updated base address register is
resuts[0]rather thanresults[1](for example).Post index immediate operands are now included as part of the memory operand in
mem.disp. Post indexing with a register however is added as an additional operand.Aliasing can be dissabled for auto-sync architectures, and has been done for AArch64. This means expected registers for the operand are now correct and allows us to remove
revertalias()from instruction_metadata completely! The only oddity is themnemonicandoperandStrare still that of the alias. This means exceptions or debugging print statements may be confusing. To indicate aliases better, anisAliasbool has been added to the metadata and exception print out.[x] Get automatic LLVM download and install working for version 18.1.8
[x]
Add AArch64 multi-vector operand enum decoding logic to instruction_decode