This introduces a capability to have 8x8 RAM tiles aligned on 64 byte boundary, placed after the VRAM. This improves blitting performance as aligned RAM tiles need one less instruction in the critical loop. When the RT_ALIGNED compile-time option is not used to enable it, the original behaviour is retained.
This introduces a capability to have 8x8 RAM tiles aligned on 64 byte boundary, placed after the VRAM. This improves blitting performance as aligned RAM tiles need one less instruction in the critical loop. When the RT_ALIGNED compile-time option is not used to enable it, the original behaviour is retained.