I am using a public library that has code that can be reduced to this:
package test is
type enum_1_t is (A_e);
subtype enum_2_1 is test.enum_1_t;
end package;
This package self reference isn't necessary, but this compiles in Vivado (synthesis and simulation) as well as Modelsim and Riviera, which suggests to me that it's valid VHDL (although I haven't looked in the standard).
VHDL LS provides the following error on the subtype declaration line:
Schottkyc137
commented
4 months ago
I am using a public library that has code that can be reduced to this:
This package self reference isn't necessary, but this compiles in Vivado (synthesis and simulation) as well as Modelsim and Riviera, which suggests to me that it's valid VHDL (although I haven't looked in the standard).
VHDL LS provides the following error on the
subtypedeclaration line: