Autocomplete for variables, records, generate statements (VSCode)

The issue might be slightly related to #289.

Recent changes to autocomplete have disabled large parts of VSCodes text based intellisense. While the filtering of the autocomplete results of vhdl-ls is a very welcome addition, it leads to a lot of typing and name lookup, if the statement is not autocompleted by vhdl-ls. I noticed the following examples which all worked before with text based intellisense.

generate statements
In generate statements neither constants for for loops nor the generate keyword itself are suggested. Only if the finale end generate is already present, the text based auto complete suggests constants or the generate keyword. Since you usually don't type end generate before the the rest, it's basically not working.
No constant completion:

No generate completion:

generate completion as text based completion with end generate already typed:
variables
Variables are not autocompleted by vhdl-ls and have to be typed manually:
records
Records are not autocompleted and as such after the . only signals are suggested. The port suggestion works:

Members of the record are not shown and have to be typed manually without text based intellisense:
calls to functions / procedures
Calls to functions and procedures are also not autocompleted by vhdl-ls and must be typed manually (no screenshot)
global constants in entity instantiations (as argument for generics)
If a constant is declared globaly in a package, it is not autocompleted when it should be used as argument for a generic in an entity instantiation. This was autocompleted by text based intellisense if the file containing the package was open somewhere, now it needs to be typed manually. Local constants declared within the same architecture are autocompleted.
Local constant autocompletion works:
Global constant autocompletion does not work:

It might be that there are more cases that I missed here.

The code used for testing is the following. If it is typed down from top to bottom without copying it, the above behavior can be observed.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

entity my_entity is
  generic (
    g_my_generic : integer
  );
  port (
    clk : in std_logic;
    reset : in std_logic
  );
end entity;

architecture rtl of my_entity is

begin

end architecture;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

package led_pkg is
  constant gc_led_cnt : positive := 8;

  type t_led_ctrl is record
    is_active : boolean;
  end record;

  constant gc_led_ctrl_init : t_led_ctrl := (
    is_active => false
  );

  type t_led_ctrl_array is array(0 to gc_led_cnt - 1) of t_led_ctrl;
  constant gc_led_array_init : t_led_ctrl_array := (others => gc_led_ctrl_init);

  constant gc_a_global_constant : integer := 5;
end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.led_pkg.all;

entity leds is
  port (
    clk   : in  std_logic;
    reset : in  std_logic;
    ctrl  : in  t_led_ctrl_array;
    btns  : in  std_logic_vector(gc_led_cnt - 1 downto 0);
    leds  : out std_logic_vector(gc_led_cnt - 1 downto 0)
  );
end entity;

architecture rtl of leds is

  constant c_a_lokal_constant : integer := 6;

begin

  i_my_entity : entity work.my_entity
  generic map (
    g_my_generic => gc_a_global_constant
  )
  port map (
    clk   => clk,
    reset => reset
  );

  gen_leds_proc : for i in 0 to gc_led_cnt - 1 generate
    do_stuff : process(clk) is
      variable v_edge_detect : std_logic := '0';
    begin
      if rising_edge(clk) then
        if reset = '1' then
          leds(i)       <= '0';
          v_edge_detect := '0';
        else
          if v_edge_detect and not btns(i) then
            if ctrl(i).is_active then
              leds(i) <= '1';
            end if;
          end if;
          v_edge_detect := btns(i);
        end if;
      end if;
    end process;
  end generate;

  gen_test : for i in 0 to gc_led_cnt - 1 generate

  end generate;
end architecture;

Edit 27.06.2024 Added global constant auto completion in entity instantiations

VHDL-LS / rust_hdl

Autocomplete for variables, records, generate statements (VSCode) #312