Cannot use predefined attributes on array subtype

[gitmodimo]

As per 16.2.3 of vhdl-2008 attributes on array subtype should be allowed.

  type test_t is record
      asdf: std_logic_vector(10 downto 0);
   end record;
   constant test: test_t;

   constant i:integer:=test.asdf'high;

   constant j:std_logic_vector(test.asdf'high downto test.asdf'low);

   constant k:std_logic_vector(test.asdf'range);

   constant l:integer:=test.asdf'high;
   constant m:std_logic_vector(test.asdf'range);

   constant ti:integer:=test_t.asdf'high;

   constant tj:std_logic_vector(test_t.asdf'high downto test_t.asdf'low);

   constant tk:std_logic_vector(test_t.asdf'range);

   constant tl:integer:=test_t.asdf'high;
   constant tm:std_logic_vector(test_t.asdf'range);

Those attributes are very useful in writting generic code and are supported at least in vivado.

[Schottkyc137]

Hi @gitmodimo Thank your for the bug report. Some of the examples that you provided are already supported. The issue that you see is due to the fact that you are declaring a constant without specifying it's value (which is not allowed). The examples 7 to 11 are a bug and should compile though. Here is an updated MRE

library ieee;
use ieee.std_logic_1164.std_logic_vector;

package foo is
    type test_t is record
        asdf: std_logic_vector(10 downto 0);
    end record;

    signal ti:integer:=test_t.asdf'high;

    signal tj:std_logic_vector(test_t.asdf'high downto test_t.asdf'low);

    signal tk:std_logic_vector(test_t.asdf'range);

    signal tl:integer:=test_t.asdf'high;

    signal tm:std_logic_vector(test_t.asdf'range);

end package;