Erroneous synthax highlighting after case-generate statements

[AndrzejKowalski9917]

If a case-generate statement is used, the synthax highlighting afterwards in the file is slightly broken. If an if-else-generate statement is used, the synthax highlighting works as expected.

1. The Label gen_sel_2 is not highlighted
2. The generate in the final end generate statement is written in italic (Theme Github Dark Dimmed - on other themes it is marked in a different color).
3. The instantiation of the following module misses synthax highlighting.

Interestingly the same error happens with syntax highlighting on github.

• VSCode Version: Version: 1.77.1
• VHDL-LS-Extension Version: v0.5.0
• VHDL-LS-Version: 0.64.0

The example code to reproduce:

package test_pkg is
  type t_selection is (
    sel_first,
    sel_second,
    sel_third
  );
end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;

use work.test_pkg.all;

entity test is
  generic (
    g_selection : t_selection
  );

  port (
    clk : in  std_logic;
    led : out std_logic
  );
end entity;

architecture rtl of test is

begin

  gen_sel : if g_selection = sel_first generate
    led <= '0';

    i_edge_detect : entity work.FallingEdgeDetector
    port map (
      clk         => clk,
      reset       => '0',
      inputSignal => '0',
      edge        => open
    );
  else generate
    led <= '1';

    i_edge_detect : entity work.RisingEdgeDetector
    port map (
      clk         => clk,
      reset       => '0',
      inputSignal => '0',
      edge        => open
    );
  end generate;

  gen_sel_2 : case g_selection generate
    when sel_first =>
      led <= '0';

      i_edge_detect : entity work.FallingEdgeDetector
      port map (
        clk         => clk,
        reset       => '0',
        inputSignal => '0',
        edge        => open
      );
    when sel_second | sel_third =>
      led <= '1';

      i_edge_detect : entity work.RisingEdgeDetector
      port map (
        clk         => clk,
        reset       => '0',
        inputSignal => '0',
        edge        => open
      );
  end generate;

  i_edge_detect : entity work.RisingEdgeDetector
  port map (
    clk         => clk,
    reset       => '0',
    inputSignal => '0',
    edge        => open
  );

end architecture;

[AndrzejKowalski9917]

Nevermind. This behavior was produced by the Verilog extension, which I also had installed. It also adds VHDL as a language to VSCode and probably does not know about this language construct. Deactivating it, fixed this issue for me.