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VHDL-LS / rust_hdl_vscode

VHDL Language Support for VSCode
MIT License
53 stars 17 forks source link

Signal of record type connected to input/output port of same record type reports a mismatch. #86

Closed singlemaltirish closed 7 months ago

singlemaltirish commented 7 months ago

I have recently started using your extension - I must say that it is great. It unimaginably increases the comfort and efficiency of work. Thanks for developing this project.

Unfortunately, I found a certain gap in functionality. Once you declare a type in package: image

Then declare an entity with input port associated with this type: image

and a signal which will be connected to this port (all based on same type): image

At the end once the connection to port is done LS is reporting an error, that the record type doesn't match: image

Could you please take a look at it? It would be nice if this could be resolved.

singlemaltirish commented 7 months ago

Addressed in rust_hdl repository: https://github.com/VHDL-LS/rust_hdl/issues/290