VHDL-LS / rust_hdl_vscode

VHDL Language Support for VSCode
MIT License
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Update vhdl.json #97

Closed sandervanthul closed 1 week ago

sandervanthul commented 2 weeks ago

fix snippets

Schottkyc137 commented 2 weeks ago

I think the intention behind having the trailing semicolon is that you usually have more signals than clk and rst and the cursor will be placed on the next line; so in most cases you would want the trailing semicolon. Do you have a use-case for your change?

sandervanthul commented 1 week ago

ah i see, that makes sense. My use case involve simple ports with only 1 input and output. Ill close this one, assuming that my use case is idiosyncratic.