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VHDL
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Interfaces
Interface definitions for VHDL-2019.
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Release plan v1.0
#6
Open
Paebbels
opened
4 years ago
Paebbels
commented
4 years ago
[x] Add Apache license text
[ ] Add contribution rules
[ ] Documentation
[x] Register
https://vhdl-interfaces.rtfd.io/
[x] Provide initial documentation skeleton - see #11
[ ] Document naming rules from #10 in documentation
[x] Add common interfaces - see #1
[x] Tristate
[x] differential signaling (P/N)
[x] differential lanes (TX/RX)
[ ] Add low-speed serial interfaces
[x] I²C - see #2
[x] I²S - see #20
[x] SPI - see #4
[ ] QSPI
[x] JTAG - see #3
[x] UART - see #15
[ ] RS232
[ ] Add low-speed parallel interfaces
[ ] LPT
[ ] ULPI
[ ] Video/Graphics
[x] VGA - see #16
[ ] DVI - request #17
[ ] HDMI - request #18
[ ] DP - request #19
[ ] LCD
MIPI
[x] C-PHY
[x] D-PHY - see #22
[x] M-PHY
[ ] Ethernet - see #21
[x] MDIO
[x] RMII
[x] MII
[x] RGMII
[x] GMII
[x] XGMII
[x] SGMII
[x] QSGMII
[x] XFI/SFI
[ ] XAUI
[ ] High Speed parallel interfaces
[ ] PCI
[ ] High Speed serial interfaces
[ ] PCI Express
[ ] Aurora
[ ] Interlaken
[x] Cages (Physical interfaces) - see #26
[x] SFP
[x] QSFP
[ ] ARM AMBA
[ ] Trace (Mictor38 Trace Bus)
[x] AXI
[x] v4
[x] AXI4 common types
[x] AXI4 (full)
[x] AXI4-Lite
[x] AXI4-Stream
[ ] Intel (Altera)
[ ] Avalon-MM - request #24
[ ] Avalon-ST - request #25
[ ] FOSSi
[ ] Wishbone - request #23
[ ] PoC
[x] CSE - see #7