VHDL / Interfaces

Interface definitions for VHDL-2019.
Other
12 stars 2 forks source link

Define tests for the interfaces #9

Open Paebbels opened 4 years ago

Paebbels commented 4 years ago

As requested by @LarsAsplund, we should also provide tests with these interfaces.

So let us discuss what we need and how we do it. Here is an initial proposal for discussion from my side.

Goals

Out of scope

Testbench Minimum Requirements

Testbench Execution Environment

Optional


/cc @LarsAsplund, @eine, @JimLewis