Silence modelsim warnings for physical.vhdl

[Paebbels]

Hello Olof,

these return values are missing by intension. But I think we have to evaluate this again. Some tools don't stop on severity failure so we forced them to stop on the missing return statement.

We forgot to add a comment line to document this behavior, like we did in other packages.

[mzabeltud]

Hello,

I evaluated it again using a simpler example. It seems that the missing return statement was required to stop XST (synthesizer of ISE) when the old parser was selected. This parser is not supported anymore. The new parser will stop with an error at the report statement with severity failure; as also Quartus (15.1) and Lattice Diamond (3.7) do.

We will have to add the return statements anyway because of Xilinx Vivado (checked with version 2016.2). Synthesis completes even if:

• the report statement with severity FAILURE is encountered in a function,
• a return statement is missing in a function (what is returned, here?),
• an assert statement with severity FAILURE fails (in my other example).

Thus users of Xilinx Vivado must rely on detecting such invalid function calls during simulation. But, the Xilinx Vivado Simulator (XSim) stops elaboration with an error regarding the missing return statement.

EDIT: The elaboration in XSim stops only if the path with the missing return is "executed". But, as the message of the report statement is not printed, one cannot easily debug it.

Regards, Martin

[Paebbels]

@mzabeltud Have you enabled asserts in your test project via TCL or project settings?

[mzabeltud]

@Paebbels Ok, missed that. After enabling assert statements, Vivado Synthesis stops during elaboration if assertion fails.