issues
search
VLSI-EDA
/
PoC
IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
https://tu-dresden.de/ing/informatik/ti/vlsi
Other
538
stars
93
forks
source link
PyInfra: Add tool support for Cadence Incisive
#37
Open
Paebbels
opened
7 years ago
Paebbels
commented
7 years ago
Add VHDL simulator support for Cadence Incisive.
Add VHDL simulator support for Cadence Incisive.