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IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
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PyInfra: Add tool support for Synopsys Synplify Pro #39

Open Paebbels opened 7 years ago

Paebbels commented 7 years ago

Add synthesizer support for Synopsys Synplify Pro.

Note:
Synplify is also included in Lattice Diamond and can be used as an alternative to the Lattice Synthesis Engine.

bergnoli commented 3 years ago

I had troubles using Synplify pro ( Microsemi ) in ocram ( true dual port ram) inference. It seems that Synplify pro does not like the multi clock processes: is that true also for other tools?

Paebbels commented 3 years ago

ocram was tested with lots of tools (ISE, Vivado, Quartus, LSE (Lattice Synthesis Engine, ...).

Please open a new issue, for your problem of how VHDL is written to specify a true dual port RAM. This issue is about Python support in using Simplify Pro.

In general, the syntax using 2 clocks in one process is correct VHDL and more over this how to write dual port RAMs. This was also specified in IEEE Std. 1076.6-2004. Normally, Simplify Pro has a very good understanding of VHDL including VHDL-2008 support for synthesis.