IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
The simulation packages are not (and will not) be supported by Xilinx ISE, because of a bad shared variable implementation. We will drop the support for VHDL-93 testbenches. We still hope for a correct VHDL-2008 in future Xilinx Vivado Simulator releases.
[ ] Rename globalSimulationStatus to globalSimStatus or SimStatus
As all global VHDL-93 variables are removed (prefixed with global_) the name can be chooses shorter.
[ ] alter sim_simulation.v08.vhdl and sim_waveform.vhdl
[ ] review all testbenches
[ ] Write a PoC.arith.prng testbench for Xilinx ISE Simulator without simulation package helper usage, so the Python infrastructure can still be tested with this testbench.
The simulation packages are not (and will not) be supported by Xilinx ISE, because of a bad shared variable implementation. We will drop the support for VHDL-93 testbenches. We still hope for a correct VHDL-2008 in future Xilinx Vivado Simulator releases.
Work Items:
sim_random.v93.vhdlsim_simulation.v93.vhdlsim_unprotected.v93.vhdl*.filesfiles.sim_random.v08.vhdl- remove commented wrappers ("procedural interface")sim_simulation.v08.vhdlglobalSimulationStatustoglobalSimStatusorSimStatusAs all global VHDL-93 variables are removed (prefixed withglobal_) the name can be chooses shorter.sim_simulation.v08.vhdlandsim_waveform.vhdl