dockerize tests

[eine]

In this PR, Travis jobs are replaced with building a docker image based on ghdl/ext:vunit. GRC is installed in the image as explained in garabik/grc. Then poc.setup.sh and poc.run.sh are executed in a container.

Note that GHDL is not built anymore. The base image which is pulled already includes both GHDL and Vunit. This should make tesks slightly faster.

Last, GHDL version is updated from 0.34-dev to 0.36-dev and mcode backend is used. This is because there is currently a single available image in https://hub.docker.com/r/ghdl/ext/tags/, including both GHDL and Python. If other images with different backends and/or Python versions are added there, the test matrix can be easily extended.

[eine]

There are two possibly legit errors now:

Testbench: PoC.fifo.ic_got
    /PoC/src/fifo/fifo_ic_got.vhdl:294:35: can't resolve overload for function call, slice or indexed name
    /PoC/src/fifo/fifo_ic_got.vhdl:294:35: possible interpretations are:
    ../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned"
    ../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"
    /PoC/src/fifo/fifo_ic_got.vhdl:294:84: can't resolve overload for function call, slice or indexed name
    /PoC/src/fifo/fifo_ic_got.vhdl:294:84: possible interpretations are:
    ../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned"
    ../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"
    /PoC/src/fifo/fifo_ic_got.vhdl:306:35: can't resolve overload for function call, slice or indexed name
    /PoC/src/fifo/fifo_ic_got.vhdl:306:35: possible interpretations are:
    ../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned"
    ../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"
    /PoC/src/fifo/fifo_ic_got.vhdl:306:84: can't resolve overload for function call, slice or indexed name
    /PoC/src/fifo/fifo_ic_got.vhdl:306:84: possible interpretations are:
    ../../src/ieee2008/numeric_std.vhdl:82:34: array subtype "unsigned"
    ../../src/ieee2008/std_logic_1164.vhdl:89:42: array subtype "std_logic_vector"
    ERROR: Error while analysing '/PoC/src/fifo/fifo_ic_got.vhdl'.
    [SKIPPED DUE TO ERRORS]

  Testbench: PoC.sim.VCDParser
    ERROR: No PoC Testbench Report in simulator output found.
    [SKIPPED DUE TO ERRORS]