IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
I need to send 1st two randomised input data into input transaction and reset =1and then reset=0.after 65th clock cycle i have to check divider output.
i am using this testbench format: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par2_cocotb.py
but reset is not toggling for every input it is constant =1.
how to toggle reset bit in this testbench.
I need to send 1st two randomised input data into input transaction and reset =1and then reset=0.after 65th clock cycle i have to check divider output. i am using this testbench format: https://github.com/VLSI-EDA/PoC/blob/master/tb/cache/cache_par2_cocotb.py but reset is not toggling for every input it is constant =1. how to toggle reset bit in this testbench.