IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany
do you know how to define the use of 512 word 16bit RAM (preloaded during FPGA power on and acting as ROM)
in vhdl (using GHDL & Yosys) for FPGA e.g. ICE40 ?
Dear,
do you know how to define the use of 512 word 16bit RAM (preloaded during FPGA power on and acting as ROM) in vhdl (using GHDL & Yosys) for FPGA e.g. ICE40 ?
Hoping to receive some help, I remain,
Patrick Pelgrims