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VLSIDA / OpenCache

An open-source custom cache generator.
BSD 3-Clause "New" or "Revised" License
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OpenRAM Failed error #4

Closed GabbedT closed 2 years ago

GabbedT commented 2 years ago

Hi, i was trying to generate a basic cache (the one described in README file). This is the config file:

# Data array size
total_size = 1024

# Data word bit size
word_size = 8

# Number of words per line
words_per_line = 4

# Address port size
address_size = 11

# Number of ways
num_ways = 1

# Replacement policy
replacement_policy = None

# Write policy
write_policy = "write-back"

# Output file name
output_name = "cache"

# Add this to OpenCache config file
openram_options = {
    "tech_name": "sky130A",
    "nominal_corner_only": True,
    "analytical_delay": False,
}

# For simulation
simulate = True

# For synthesis
synthesize = True

# To keep the results
keep_temp = True

Then i execute the command: python3 opencache.py my_config.py inside generator folder. The output is:

** Start: 07/06/2022 22:21:32

Cache type: Data
Word size: 8
Words per line: 4
Number of ways: 1
Replacement policy: None
Write policy: None
Return type: Word
Data hazard: True

Saving output files...
Config: Writing to /home/gabriele/OpenCache/generator/outputs/cache/cache_data_array_config.py
Config: Writing to /home/gabriele/OpenCache/generator/outputs/cache/cache_tag_array_config.py
** Config: 0.0 seconds
Verilog: Writing to /home/gabriele/OpenCache/generator/outputs/cache/cache.v
** Verilog: 0.1 seconds
Initializing verification...
ERROR: file verification.py: line 167: OpenRAM failed!
Traceback (most recent call last):
  File "opencache.py", line 61, in <module>
    verify.run(cache_config=conf, name=OPTS.output_name)
  File "/home/gabriele/OpenCache/generator/verify/__init__.py", line 34, in run
    ver.verify()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 48, in verify
    self.prepare_files()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 144, in prepare_files
    self.run_openram("{}_config.py".format(OPTS.temp_path + OPTS.data_array_name))
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 167, in run_openram
    debug.error("OpenRAM failed!", -1)
  File "/home/gabriele/OpenCache/generator/debug.py", line 47, in error
    assert return_value == 0
AssertionError

I also tried to modify simulate = True to simulate = False but nothing changes.

erendn commented 2 years ago

Hello Gabriele,

Sorry for the late reply. Can you run it again with the following command inside the generator folder:

python3 opencache.py my_config.py -v -v

This command should print the output of OpenRAM so that we can identify the issue.

Best, Eren

GabbedT commented 2 years ago

@erendn Hi, i did as you said, this is the output now

Technology: sky130A
Total size: 1024 bits
Word size: 32
Words: 32
Banks: 1
Write size: None
RW ports: 0
R-only ports: 1
W-only ports: 1
Netlist only mode (no physical design is being done, netlist_only=False to disable).
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Performing simulation-based characterization with ngspice
Trimming netlist to speed up characterization (trim_netlist=False to disable).
Only generating nominal corner timing.
Traceback (most recent call last):
  File "/home/gabriele/OpenRAM/compiler/openram.py", line 54, in <module>
    c = sram_config(word_size=OPTS.word_size,
  File "/home/gabriele/OpenRAM/compiler/sram/sram_config.py", line 44, in __init__
    self.compute_sizes()
  File "/home/gabriele/OpenRAM/compiler/sram/sram_config.py", line 58, in compute_sizes
    bitcell = factory.create(module_type=OPTS.bitcell)
  File "/home/gabriele/OpenRAM/compiler/sram_factory.py", line 145, in create
    obj = mod(name=module_name, **kwargs)
  File "/home/gabriele/OpenRAM/compiler/bitcells/pbitcell.py", line 53, in __init__
    self.create_layout()
  File "/home/gabriele/OpenRAM/compiler/bitcells/pbitcell.py", line 69, in create_layout
    self.calculate_spacing()
  File "/home/gabriele/OpenRAM/compiler/bitcells/pbitcell.py", line 248, in calculate_spacing
    + self.poly_to_contact + 2 * contact.poly_contact.width \
AttributeError: 'pbitcell' object has no attribute 'poly_to_contact'. Did you mean: 'poly_to_poly_contact'?
ERROR: file verification.py: line 167: OpenRAM failed!
Traceback (most recent call last):
  File "/home/gabriele/OpenCache/generator/opencache.py", line 61, in <module>
    verify.run(cache_config=conf, name=OPTS.output_name)
  File "/home/gabriele/OpenCache/generator/verify/__init__.py", line 34, in run
    ver.verify()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 48, in verify
    self.prepare_files()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 144, in prepare_files
    self.run_openram("{}_config.py".format(OPTS.temp_path + OPTS.data_array_name))
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 167, in run_openram
    debug.error("OpenRAM failed!", -1)
  File "/home/gabriele/OpenCache/generator/debug.py", line 47, in error
    assert return_value == 0
AssertionError
erendn commented 2 years ago

This looks like an internal error of OpenRAM but I think yours is an old version. I updated mine to v1.2.0 and couldn't reproduce this error. Can you try again after updating your OpenRAM to the latest stable version?

GabbedT commented 2 years ago

@erendn I installed the latest OpenRAM version and followed the instructions in the README file (I also did the SKY130 setup). I tried to modify the tech_name in openram_options:

openram_options = {
    "tech_name": "sky130",  <- Instead of sky130A 
    "nominal_corner_only": True,
    "analytical_delay": False,
}

This is the new output:

Traceback (most recent call last):
  File "/home/gabriele/OpenRAM/compiler/openram.py", line 35, in <module>
    g.init_openram(config_file=args[0], is_unit_test=False)
  File "/home/gabriele/OpenRAM/compiler/globals.py", line 202, in init_openram
    import_tech()
  File "/home/gabriele/OpenRAM/compiler/globals.py", line 560, in import_tech
    tech_mod = __import__(OPTS.tech_name)
  File "/home/gabriele/OpenRAM/technology/sky130/__init__.py", line 26, in <module>
    raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.")
SystemError: Unable to find open_pdks tech file. Set PDK_ROOT.
ERROR: file verification.py: line 167: OpenRAM failed!
Traceback (most recent call last):
  File "/home/gabriele/OpenCache/generator/opencache.py", line 61, in <module>
    verify.run(cache_config=conf, name=OPTS.output_name)
  File "/home/gabriele/OpenCache/generator/verify/__init__.py", line 34, in run
    ver.verify()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 48, in verify
    self.prepare_files()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 144, in prepare_files
    self.run_openram("{}_config.py".format(OPTS.temp_path + OPTS.data_array_name))
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 167, in run_openram
    debug.error("OpenRAM failed!", -1)
  File "/home/gabriele/OpenCache/generator/debug.py", line 47, in error
    assert return_value == 0
AssertionError

I understand that I didn't set the PDK_ROOT variable and I don't know which path should i set as PDK_ROOT.

erendn commented 2 years ago

As far as I understand, you need to set $PDK_ROOT to the directory you want to install PDK files using the make pdk command when you are installing SKY130. I think you can set it as any path you want.

You can use other PDKs too as some of them are already provided in the OpenRAM project if I am not wrong.

Let me know if this issue persists after you set $PDK_ROOT.

GabbedT commented 2 years ago

@erendn I figured out that when i executed make pdk i didn't have $PDK_ROOT set, so everything is installed in $HOME/OpenRAM (i guess), now the output is different:

  File "/home/gabriele/OpenRAM/compiler/openram.py", line 35, in <module>
    g.init_openram(config_file=args[0], is_unit_test=False)
  File "/home/gabriele/OpenRAM/compiler/globals.py", line 202, in init_openram
    import_tech()
  File "/home/gabriele/OpenRAM/compiler/globals.py", line 560, in import_tech
    tech_mod = __import__(OPTS.tech_name)
  File "/home/gabriele/OpenRAM/technology/sky130/__init__.py", line 32, in <module>
    raise SystemError("Did not find {} under {}".format(sky130_lib_ngspice, open_pdks))
SystemError: Did not find /home/gabriele/OpenRAM/open_pdks/sky130/sky130A/sky130A/libs.tech/ngspice/sky130.lib.spice under /home/gabriele/OpenRAM/open_pdks/sky130/sky130A/sky130A/libs.tech
ERROR: file verification.py: line 167: OpenRAM failed!
Traceback (most recent call last):
  File "/home/gabriele/OpenCache/generator/opencache.py", line 61, in <module>
    verify.run(cache_config=conf, name=OPTS.output_name)
  File "/home/gabriele/OpenCache/generator/verify/__init__.py", line 34, in run
    ver.verify()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 48, in verify
    self.prepare_files()
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 144, in prepare_files
    self.run_openram("{}_config.py".format(OPTS.temp_path + OPTS.data_array_name))
  File "/home/gabriele/OpenCache/generator/verify/verification.py", line 167, in run_openram
    debug.error("OpenRAM failed!", -1)
  File "/home/gabriele/OpenCache/generator/debug.py", line 47, in error
    assert return_value == 0
AssertionError

I manually checked the file and it was there, however i don't understand why the folder sky130A is repeated two times: /home/gabriele/OpenRAM/open_pdks/sky130/sky130A/sky130A/libs.tech/ngspice/sky130.lib.spice

erendn commented 2 years ago

I inspected the code and I think your $PDK_ROOT is /home/gabriele/OpenRAM/open_pdks/sky130/sky130A although OpenRAM expects it to be /home/gabriele/OpenRAM/open_pdks/sky130 since it adds a "sky130A" to the path.

GabbedT commented 2 years ago

@erendn I fixed $PDK_ROOT and now the flow get stuck in:

Netlist only mode (no physical design is being done, netlist_only=False to disable).
DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).
Performing simulation-based characterization with ngspice
Trimming netlist to speed up characterization (trim_netlist=False to disable).
Only generating nominal corner timing.
Words per row: 1
Output files are: 
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.lvs
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.sp
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.v
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.lib
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.py
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.html
/home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.log
** Submodules: 0.1 seconds
** SRAM creation: 0.1 seconds
SP: Writing to /home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.sp
** Spice writing: 0.1 seconds
LVS: Writing to /home/gabriele/OpenCache/generator/outputs/cache/tmp/cache_data_array.lvs.sp
** LVS writing: 0.0 seconds
LIB: Characterizing...
erendn commented 2 years ago

Characterization might take a long time, depending on the system and configuration but this is a simple design so it shouldn't take a long time. You can change your config file to this:

openram_options = {
    "tech_name": "sky130", 
    "nominal_corner_only": True,
    "analytical_delay": False,
    "verbose_level": 3,
}

OpenRAM will print more elaborate output and we can understand if it actually gets stuck somewhere.

GabbedT commented 2 years ago

@erendn It gets stuck here: [characterizer.stimuli/run_sim]: /usr/bin/ngspice -b -o /tmp/openram_gabriele_5791_temp/timing.lis /tmp/openram_gabriele_5791_temp/delay_stim.sp

No warnings or error seems to appear in the output.

erendn commented 2 years ago

Apparently, OpenRAM is running a simulation using ngspice. There is a recent issue in the OpenRAM repo (https://github.com/VLSIDA/OpenRAM/issues/152). This issue might be related to that one. They also discussed this in the slack workspace of OpenRAM and it looks like they fixed the problem. They needed to point $FREEPDK45 to the installed package of it. However, that issue is about freepdk45 and you are using sky130. So, there might be a problem with the sky130 setup.

GabbedT commented 2 years ago

@erendn Ok, thank you for the support!