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VLSIDA / OpenRAM

An open-source static random access memory (SRAM) compiler.
http://www.openram.org
BSD 3-Clause "New" or "Revised" License
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Verilog files issue #124

Closed nayiri-k closed 2 years ago

nayiri-k commented 2 years ago

I'm trying to use the verilog files generated for the Sky130 SRAMs, but I encounter an error during RTL simulation. It seems the mem signal is used before it is declared (via this declaration: reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];). Moving this declaration before mem is referenced resolved the error in my simulation.

I am assuming that the open-source simulator used to verify the verilog files doesn't treat undeclared signals as an error, so this issue wasn't detected.

mguthaus commented 2 years ago

Thanks, this should be fixed in e6a009312e7965b87c9b0af9e36c3ffffd7b9179 in the dev branch.

Yes, none of the open-source simulators seem to complain about this, so we didn't catch it. Thanks for pointing it out!