I'm trying to use the verilog files generated for the Sky130 SRAMs, but I encounter an error during RTL simulation. It seems the mem signal is used before it is declared (via this declaration: reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];). Moving this declaration before mem is referenced resolved the error in my simulation.
I am assuming that the open-source simulator used to verify the verilog files doesn't treat undeclared signals as an error, so this issue wasn't detected.
I'm trying to use the verilog files generated for the Sky130 SRAMs, but I encounter an error during RTL simulation. It seems the
mem
signal is used before it is declared (via this declaration:reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
). Moving this declaration beforemem
is referenced resolved the error in my simulation.I am assuming that the open-source simulator used to verify the verilog files doesn't treat undeclared signals as an error, so this issue wasn't detected.