Does OpenRAM support bit enable ? How to configure ?

[mguthaus]

Do you mean bit write? This is the write_size parameter that configures how many bits should exist in the mask. If the and gate that does the masking is narrower than the bitcell in a given technology, it can be bitwise masked. We have generally supplied byte write masks which are most frequently used.

[mguthaus]

Please see the following example that uses byte write. You can change write_size to 1 to get byte write: https://github.com/VLSIDA/OpenRAM/blob/stable/macros/configs/sky130_sram_2kbyte_1rw1r_32x512_8.py

[szuhzw]

I tried to write write_size to 1, but it would report error when runing.

[szuhzw]

It's ok to write write_size to 8.

[mguthaus]

If the and gate that does the masking is narrower than the bitcell in a given technology, it can be bitwise masked. This means it isn't so you would need to make a custom and gate to do it.

[mguthaus]

The error would say this...

[szuhzw]

So, you means the OpenRAM cannot support bite write at present?

[mguthaus]

It supports it but not in that technology. It depends on the width of the and gate compared to the width of the bitcell which is different in each technology. You could add an improved and cell to fix this.

[szuhzw]

OK,Thank you

------------------ 原始邮件 ------------------ 发件人: "Matt @.>; 发送时间: 2022年7月22日(星期五) 中午1:20 收件人: @.>; 抄送: @.>; @.>; 主题: Re: [VLSIDA/OpenRAM] Does OpenRAM support bit enable ? How to configure ? (Issue #148)

It supports it but not in that technology. It depends on the width of the and gate compared to the width of the bitcell which is different in each technology. You could add an improved and cell to fix this.

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