Closed Ruiggg closed 1 year ago
CACTI isn't a real memory. It is an estimate based on models so it is likely quite wrong. While OpenRAM won't be the most efficient compared to a hand tuned memory array, it is an actual design.
@Ruiggg I failed to get the area from CACTI7 due to the error: ERROR: no valid data array organizations found
would you help me with CACTI7?
Describe the bug I have generated a SRAM whose size is 16 Row * 512 bit,the area is 0.35 mm^2 (using freePDK-45nm). However, I generated the same size of SRAM in CACTI, the area is only 0.028 mm^2. (more than 10X smaller than 0.35 mm^2)
Version The openRAM is from https://hub.docker.com/r/vlsida/openram-ubuntu/tags The CACTI version is 7
To Reproduce To use Openram:
To use CACTI:
Expected behavior We expect the two area are close because both technologies are 45nm. However, the area from OpenRAM is over 10X than that from CACTI.
Logs The Output of OpenRAM:
sram_512_16_freepdk45.html
Compiled at: 2023-02-03
DRC errors: skipped
LVS errors: skipped
Git commit id: 5ad1db95a80e04c541bf16d59678375a60734807
Ports and Configuration
Operating Conditions
Timing Data
Using analytical model: results may not be precise
Power Data
Characterization Corners
Deliverables
Operating Conditions
Timing Data
Using analytical model: results may not be precise
Power Data
Characterization Corners
Deliverables
The Output of CACTI: line_sz: 64 Cache size : 1024 Block size : 64 Associativity : 1 Read only ports : 0 Write only ports : 0 Read write ports : 1 Single ended read ports : 0 Cache banks (UCA) : 1 Technology : 0.045 Temperature : 360 Tag size : 42 array type : Scratch RAM Model as memory : 0 Model as 3D memory : 0 Access mode : 0 Data array cell type : 2 Data array peripheral type : 2 Tag array cell type : 2 Tag array peripheral type : 2 Optimization target : 2 Design objective (UCA wt) : 100 20 20 10 10 Design objective (UCA dev) : 10 1000 1000 1000 1000 Cache model : 0 Nuca bank : 0 Wire inside mat : 1 Wire outside mat : 1 Interconnect projection : 1 Wire signaling : 0 Print level : 1 ECC overhead : 0 Page size : 8192 Burst length : 8 Internal prefetch width : 8 Force cache config : 0 Subarray Driver direction : 1 iostate : WRITE dram_ecc : NO_ECC io_type : DDR3 dram_dimm : UDIMM IO Area (sq.mm) = inf IO Timing Margin (ps) = -14.1667 IO Votlage Margin (V) = 0.155 IO Dynamic Power (mW) = 1506.36 PHY Power (mW) = 232.752 PHY Wakeup Time (us) = 27.503 IO Termination and Bias Power (mW) = 2505.96
---------- CACTI (version 7.0.3DD Prerelease of Aug, 2012), Uniform Cache Access SRAM Model ----------
Cache Parameters: Total cache size (bytes): 1024 Number of banks: 1 Associativity: direct mapped Block size (bytes): 64 Read/write Ports: 1 Read ports: 0 Write ports: 0 Technology size (nm): 45
Time Components:
Data side (with Output driver) (ns): 0.328414 H-tree input delay (ns): 0 Decoder + wordline delay (ns): 0.219156 Bitline delay (ns): 0.0221284 Sense Amplifier delay (ns): 0.0045617 H-tree output delay (ns): 0.0825678
Power Components:
Data array: Total dynamic read energy/access (nJ): 0.0121486 Total energy in H-tree (that includes both address and data transfer) (nJ): 0 Output Htree inside bank Energy (nJ): 0 Decoder (nJ): 4.86508e-05 Wordline (nJ): 0 Bitline mux & associated drivers (nJ): 0 Sense amp mux & associated drivers (nJ): 0.000144445 Bitlines precharge and equalization circuit (nJ): 0.00109084 Bitlines (nJ): 0.000486859 Sense amplifier energy (nJ): 0.000962157 Sub-array output driver (nJ): 0.00941569 Total leakage power of a bank (mW): 0.022123 Total leakage power in H-tree (that includes both address and data network) ((mW)): 0 Total leakage power in cells (mW): 0 Total leakage power in row logic(mW): 0 Total leakage power in column logic(mW): 0 Total gate leakage power in H-tree (that includes both address and data network) ((mW)): 0
Area Components:
Data array: Area (mm2): 0.0283078 Height (mm): 0.116263 Width (mm): 0.24348 Area efficiency (Memory cell area/Total area) - 8.55583 % MAT Height (mm): 0.116263 MAT Length (mm): 0.24348 Subarray Height (mm): 0.005256 Subarray Length (mm): 0.1206 [MARK] GHR 1
Wire Properties:
Delay Optimal Repeater size - 61.34 Repeater spacing - 0.15395 (mm) Delay - 0.240487 (ns/mm) PowerD - 0.000265471 (nJ/mm) PowerL - 0.000392114 (mW/mm) PowerLgate - 0.00303194 (mW/mm) Wire width - 0.045 microns Wire spacing - 0.045 microns
5% Overhead Repeater size - 32.34 Repeater spacing - 0.15395 (mm) Delay - 0.251597 (ns/mm) PowerD - 0.000185205 (nJ/mm) PowerL - 0.000206732 (mW/mm) PowerLgate - 0.00159851 (mW/mm) Wire width - 0.045 microns Wire spacing - 0.045 microns
10% Overhead Repeater size - 33.34 Repeater spacing - 0.25395 (mm) Delay - 0.264482 (ns/mm) PowerD - 0.000168422 (nJ/mm) PowerL - 0.000129201 (mW/mm) PowerLgate - 0.000999019 (mW/mm) Wire width - 0.045 microns Wire spacing - 0.045 microns
20% Overhead Repeater size - 25.34 Repeater spacing - 0.25395 (mm) Delay - 0.284786 (ns/mm) PowerD - 0.000152588 (nJ/mm) PowerL - 9.8199e-05 (mW/mm) PowerLgate - 0.000759302 (mW/mm) Wire width - 0.045 microns Wire spacing - 0.045 microns
30% Overhead Repeater size - 20.34 Repeater spacing - 0.25395 (mm) Delay - 0.30947 (ns/mm) PowerD - 0.000143076 (nJ/mm) PowerL - 7.88227e-05 (mW/mm) PowerLgate - 0.000609479 (mW/mm) Wire width - 0.045 microns Wire spacing - 0.045 microns
Low-swing wire (1 mm) - Note: Unlike repeated wires, delay and power values of low-swing wires do not have a linear relationship with length. delay - 0.304043 (ns) powerD - 4.32079e-06 (nJ) PowerL - 9.84723e-09 (mW) PowerLgate - 1.38271e-07 (mW) Wire width - 9e-08 microns Wire spacing - 9e-08 microns
top 3 best memory configurations are: Memory cap: 80 GB num_bobs: 1 bw: 533 (MHz) cost: $731.2 energy: 32.6101 (nJ) { (0) BoB cap: 80 GB num_channels: 1 bw: 533 (MHz) cost: $731.2 energy: 32.6101 (nJ)
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