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VLSIDA / OpenRAM

An open-source static random access memory (SRAM) compiler.
http://www.openram.org
BSD 3-Clause "New" or "Revised" License
780 stars 198 forks source link

multiports bitcell #233

Closed YWJ226 closed 3 months ago

YWJ226 commented 3 months ago

Hi, I saw on the official website of OpenRAM that it supports generating multi-port devices, and the displayed bitcell structure supports at least three ports. However, when I tried to generate a three-port device, I found that the bank.py file only supports up to two ports. Could you please tell me how to modify it to generate a three-port bitcell, or are there any related documents available?

mguthaus commented 3 months ago

It can generate the netlist but the top level layout is not possible due to the arrangement of the ports. We assume one goes on the left/bottom and the other on the top/right.