search

VLSIDA / OpenRAM

An open-source static random access memory (SRAM) compiler.
http://www.openram.org
BSD 3-Clause "New" or "Revised" License
780 stars 198 forks source link

Not generate certain module #244

Closed YWJ226 closed 3 weeks ago

YWJ226 commented 3 weeks ago

Describe the bug Hello, I encountered some issues while using OpenRAM and I'm looking forward to your assistance.

  1. Does OpenRAM support the option to not generate certain modules, such as excluding the decoder part within the entire SRAM?
  2. If I need to add custom modules, can I simply add them to the technology library file without modifying anything in the Compiler folder? For example, if I want to include a TSV module within the decoder module, can I add TSV as a custom module under my 3D technology library?

Version 1.2.48

mguthaus commented 3 weeks ago

There are two ways to customize modules:

1) At the technology library level, you can add a python file in the "modules" subdirectory and then add a line like this to your technology config:

tech_modules["col_cap_array"] = ["sky130_col_cap_array", "col_cap_array"]

In the case of a two item list, the first is for single port and the second is for dual port. Otherwise, a single item is used for both.

2) You can add a customized module in your user configuration for an SRAM: bitcell = "bitcell_1rw_1r" would use a custom bitcell, for example. More at: https://github.com/VLSIDA/OpenRAM/blob/stable/docs/source/basic_usage.md#common-configuration-file-options