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VLSIDA / OpenRAM

An open-source static random access memory (SRAM) compiler.
http://www.openram.org
BSD 3-Clause "New" or "Revised" License
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Assertion Error in SRAM Generation with Specific word_size and num_words Configurations #251

Open riagus99 opened 1 month ago

riagus99 commented 1 month ago

Describe the bug I attempted to generate an SRAM instance using the following command:

python $OPENRAM_HOME/../sram_compiler.py myconfig.py

While some configurations work perfectly, others fail to execute. I'm not sure if I'm using an unsupported configuration or if this could be a bug in OpenRAM.

Below, I've listed the configurations that work and those that do not.

Working configurations

Not working configurations

Version commit b6a6f12

To Reproduce As an example, here is the configuration that fails (word_size = 32, num_words = 100).

python version: Python 3.8.19

configuration file (myconfig.py)

num_rw_ports    = 1
num_r_ports     = 0
num_w_ports     = 0

# Number of bits per word
word_size = 32
# Number of words (some people call this 'depth')
num_words = 100

# The fabrication technology. This must match the PDK name in $OPENRAM_TECH.
tech_name = "freepdk45"

# Process corners, temperature and voltage to characterize
process_corners = ["TT"]
supply_voltages = [0.9]
temperatures = [40]
nominal_corner_only = True

route_supplies  = False
#check_lvsdrc = True

#output_path     = "SRAM_{0}x{1}_r1_w1".format(word_size, num_words)
#output_name     = "SRAM_{0}x{1}_r1_w1".format(word_size, num_words)
#instance_name   = "SRAM_{0}x{1}_r1_w1".format(word_size, num_words)
output_path     = "SRAM_{0}x{1}_rw{2}_r{3}_w{4}".format(word_size, num_words, num_rw_ports, num_r_ports, num_w_ports)
output_name     = "SRAM_{0}x{1}_rw{2}_r{3}_w{4}".format(word_size, num_words, num_rw_ports, num_r_ports, num_w_ports)
instance_name     = "SRAM_{0}x{1}_rw{2}_r{3}_w{4}".format(word_size, num_words, num_rw_ports, num_r_ports, num_w_ports)

Logs Below is the output I received:

|==============================================================================|
|=========                      OpenRAM v1.2.48                       =========|
|=========                                                            =========|
|=========               VLSI Design and Automation Lab               =========|
|=========        Computer Science and Engineering Department         =========|
|=========            University of California Santa Cruz             =========|
|=========                                                            =========|
|=========          Usage help: openram-user-group@ucsc.edu           =========|
|=========        Development help: openram-dev-group@ucsc.edu        =========|
|=========                See LICENSE for license info                =========|
|==============================================================================|
** Start: 08/18/2024 07:42:04
Technology: freepdk45
Total size: 3200 bits
Word size: 32
Words: 100                                                                                                                                                                                                                                                                                                                                                           Banks: 1                                                                                                                                                                                                                                                                                                                                                             RW ports: 1                                                                                                                                                                                                                                                                                                                                                          R-only ports: 0                                                                                                                                                                                                                                                                                                                                                      W-only ports: 0                                                                                                                                                                                                                                                                                                                                                      Design supply routing skipped. Supplies will have multiple must-connect pins. (route_supplies=True to enable supply routing).                                                                                                                                                                                                                                        DRC/LVS/PEX is only run on the top-level design to save run-time (inline_lvsdrc=True to do inline checking).
DRC/LVS/PEX is disabled (check_lvsdrc=True to enable).                                                                                                                                                                                                                                                                                                               Characterization is disabled (using analytical delay models) (analytical_delay=False to simulate).                                                                                                                                                                                                                                                                   Only generating nominal corner timing.                                                                                                                                                                                                                                                                                                                               Words per row: None                                                                                                                                                                                                                                                                                                                                                  Output files are:                                                                                                                                                                                                                                                                                                                                                    /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.lvs                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.sp
/root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.v                                                                                                                                                                                                                                                                                            /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.lib                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.py                                                                                                                                                                                                                                                                                           /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.html                                                                                                                                                                                                                                                                                         /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.log                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.lef                                                                                                                                                                                                                                                                                          /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.gds
** Submodules: 15.0 seconds
** Placement: 0.1 seconds
** Routing: 140.9 seconds
** Verification: 0.0 seconds
** SRAM creation: 155.9 seconds
SP: Writing to /root/verilog_works/OpenRAM/SRAM_32x100_rw1_r0_w0/SRAM_32x100_rw1_r0_w0.sp
** Spice writing: 0.3 seconds
DELAY: Writing stimulus...                                                                                                                        ERROR: file simulation.py: line 606: Could not find bl net in timing paths.                                                                                                                                                                                                                                                                                          Traceback (most recent call last):                                                                                                                                                                                                                                                                                                                                     File "/root/verilog_works/OpenRAM/compiler/../sram_compiler.py", line 76, in <module>                                                                                                                                                                                                                                                                                  s.save()                                                                                                                                                                                                                                                                                                                                                           File "/root/verilog_works/OpenRAM/compiler/sram.py", line 130, in save                                                                                                                                                                                                                                                                                                 d.analysis_init(probe_address, probe_data)
  File "/root/verilog_works/OpenRAM/compiler/characterizer/delay.py", line 1288, in analysis_init                                                                                                                                                                                                                                                                        self.set_internal_spice_names()                                                                                                                                                                                                                                                                                                                                    File "/root/verilog_works/OpenRAM/compiler/characterizer/simulation.py", line 520, in set_internal_spice_names                                                                                                                                                                                                                                                         bl_name_port, br_name_port = self.get_bl_name(self.graph.all_paths, port)                                                                                                                                                                                                                                                                                          File "/root/verilog_works/OpenRAM/compiler/characterizer/simulation.py", line 625, in get_bl_name                                                                                                                                                                                                                                                                      bl_names.append(self.get_alias_in_path(paths, int_net, cell_mod, exclude_set))                                                                                                                                                                                                                                                                                     File "/root/verilog_works/OpenRAM/compiler/characterizer/simulation.py", line 606, in get_alias_in_path
    debug.error("Could not find {} net in timing paths.".format(internal_net), 1)                                                                                                                                                                                                                                                                                      File "/root/verilog_works/OpenRAM/compiler/debug.py", line 48, in error                                                                                                                                                                                                                                                                                                assert return_value == 0                                                                                                                                                                                                                                                                                                                                         AssertionError

Additional context I have reviewed the documentation but could not find any constraints related to the configuration that could explain this issue. If there are specific constraints that I should be aware of, could you please provide some guidance?

mguthaus commented 1 month ago

Yes, this is a duplicate of https://github.com/VLSIDA/OpenRAM/issues/228