Update README for wishbone - Githubissues

VLSIDA / openram_testchip2

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Update README for wishbone #5

Closed mguthaus closed 1 year ago

mguthaus commented 1 year ago

Wishbone is listed as single port only and a WIP.

https://github.com/VLSIDA/openram_testchip2#wishbone-mode-wip

hadirkhan10 commented 1 year ago

closed in bb692d6