search

VLSIDA / sky130_sram_macros

Apache License 2.0
6 stars 9 forks source link

using Verilog code in Modelsim #1

Closed mbaykenar closed 2 years ago

mbaykenar commented 2 years ago

I want to change memory modules in a design with OpenRAM macros such as sky130_sram_2kbyte_1rw1r_32x512_8.v

I first need adapt pins and R/W functionalities of OpenRAM to our memory access port of a RISC-V core.

Just want to ask, what is the right path for this integration: First take Verilog code of OpenRAM macro and then add to our design. Then do functional simulation via Modelsim for example. If functional simulation is OK, then i will start OpenLane flow?

mguthaus commented 2 years ago

This isn't really an issue with the memories... You can ask help questions either on the OpenRAM mail lists (see the README)or in the OpenRAM or skywater slack (#openram).

I'm not clear what you want. You shouldn't modify the Verilog at all as this is an output from the memory compiler. If you want a different size or configuration, you need to run the compiler to generate it. Hope this helps.