Add support for Vivado XSIM

[LarsAsplund]

We have started to do some work but we didn't have an issue for it so I'm creating one.

[Piressss]

I'm not sure if the GHDL is a homologated tool by the IT team here.

Let me ask you a question. I created the environment variable VUNIT_XSIM_PATH and VUNIT_SIMULATOR = xsim.

When I try to compile, I get the following error:

  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\ui\__init__.py", line 683, in main
    all_ok = self._main(post_run)
  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\ui\__init__.py", line 727, in _main
    return self._main_compile_only()
  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\ui\__init__.py", line 865, in _main_compile_only
    simulator_if = self._create_simulator_if()
  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\ui\__init__.py", line 749, in _create_simulator_if
    args=self._args, output_path=self._simulator_output_path
  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\sim_if\xsim_interface.py", line 47, in from_args
    return cls(prefix=prefix, output_path=output_path, gui=args.gui)
  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\sim_if\xsim_interface.py", line 67, in __init__
    self._xvlog = self.check_tool('xvlog')
  File "C:/Users/fepires/Downloads/vunit-xsim-rebase-v2\vunit\sim_if\xsim_interface.py", line 61, in check_tool
    raise Exception('Cannot find %s' % tool_name)
Exception: Cannot find xvlog

Have you already see it before?

[eine]

I'm not sure if the GHDL is a homologated tool by the IT team here.

Actually, GHDL can be extracted/built to a user directory, so it can be used without admin permissions. Anyway, you might want to ask the IT team about it. GHDL is available in several distribution repositories, and they might consider to add it. As a matter of fact, GHDL and VUnit are used as a complement to vendor tools in many companies/institutions without managers being aware. I'm NOT enforcing you to go against any rule, but just letting you know that adoption of VUnit and GHDL is done bottom-to-top in many organisations.

Let me ask you a question. I created the environment variable VUNIT_XSIM_PATH and VUNIT_SIMULATOR = xsim.

Which is the content of VUNIT_XSIM_PATH? Is it pointing to a directory or a binary?

[Piressss]

I'm not sure if the GHDL is a homologated tool by the IT team here.

Actually, GHDL can be extracted/built to a user directory, so it can be used without admin permissions. Anyway, you might want to ask the IT team about it. GHDL is available in several distribution repositories, and they might consider to add it. As a matter of fact, GHDL and VUnit are used as a complement to vendor tools in many companies/institutions without managers being aware. I'm NOT enforcing you to go against any rule, but just letting you know that adoption of VUnit and GHDL is done bottom-to-top in many organisations.

Let me ask you a question. I created the environment variable VUNIT_XSIM_PATH and VUNIT_SIMULATOR = xsim.

Which is the content of VUNIT_XSIM_PATH? Is it pointing to a directory or a binary?

I found the problem, is the VUNIT_XSIM_PATH, I typed wrong path.

[Piressss]

Another question.

I got the following error:

ERROR: [XSIM 43-4316] Can not find file: E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\sync_lib

The path library was not created, but I can see a directory called 'xsim.dir' at the same level of 'vunit_out':

    Directory: E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\xsim.dir

Mode                LastWriteTime         Length Name
----                -------------         ------ ----
d-----        3/23/2020   1:33 PM                sync_lib

Is it correct?

[qarlosalberto]

Could you share your run.py?

[Piressss]

#!/usr/bin/env python
import sys, os, subprocess, shutil
import os.path as p
#from vunit import VUnit
from data_checker import ZeroSamplesChecker

sys.path.append('C:/Users/fepires/Downloads/vunit-xsim-rebase-v2/')

from vunit import VUnit, VUnitCLI
from vunit.sim_if.factory import SIMULATOR_FACTORY

def main():
    root_dir = p.join(p.dirname(__file__), '..', '..', '..', '..', '..')
    #root_dir = root_dir.replace("\\", "/")
    lib_path = p.join(p.dirname(__file__), '..')
    lib_path = lib_path.replace("\\", "/")

    vhdl_standard = '2008'

    # Check Vsim 
    simulator_class = SIMULATOR_FACTORY.select_simulator()
    simname = simulator_class.name
    print(simname)

    # Verify the version of the Modelsim
    mver = os.environ['MSIM_VER']
    if not os.path.isfile('msim_ver.log'):
        ofile=open('msim_ver.log','w')
        ofile.write(mver)
        ofile.close()
        if os.path.exists('vunit_out/'):
            shutil.rmtree('./vunit_out')
    else:
        ifile=open('msim_ver.log','r')
        tmp = ifile.readline()
        ifile.close()
        if mver != tmp:
            print("ModelSim version changed since the last run")
            ofile=open('msim_ver.log','w')
            ofile.write(mver)
            ofile.close()
            if os.path.exists('vunit_out/'):
                shutil.rmtree('./vunit_out')

    # Path da XILINX
    xilinx_path = os.environ['XILINX_VIVADO']
    xilinx_path = xilinx_path.replace("\\", "/")

    ui = VUnit.from_argv()
    ui.add_com()

    # Adding testbenchs. Its name must end with '_tb'
    lib = ui.add_library("axi_stream_lib_tb", vhdl_standard)
    # TB
    lib.add_source_file(p.join(lib_path, 'simul', "axi_length_adjust_tb.vhd"))
    add_axi_length_adjust_test(lib.entity("axi_length_adjust_tb"))

    lib.add_source_file("axi_frame_repeater_tb.vhd")
    frame_repeater_test(lib.entity("axi_frame_repeater_tb"))

    lib.add_source_file("axis_accum_tb.vhd")
    add_axis_accum_test(lib.entity("axis_accum_tb"))

    lib.add_source_file("axi_truncate_tb.vhd")
    truncate_test(lib.entity("axi_truncate_tb"))

    lib.add_source_file("axi_stream_insert_tlast_tb.vhd")
    add_axi_stream_insert_tlast_test(lib.entity("axi_stream_insert_tlast_tb"))
    lib.add_source_file("axis_sync_fifo_tb.vhd")
    add_axis_sync_fifo_test(lib.entity("axis_sync_fifo_tb"))

    lib.add_source_file("axis_gen_pckg_tb.vhd")
    add_axis_gen_pckg_test(lib.entity("axis_gen_pckg_tb"))
    lib.add_source_file("axi_frame_decimation_tb.vhd")
    add_axi_frame_decimation_test(lib.entity("axi_frame_decimation_tb"))

    lib.add_source_file("axis_zero_samples_tb.vhd")
    add_axis_zero_samples_test(lib.entity("axis_zero_samples_tb"))

    lib.add_source_file(xilinx_path + "/data/verilog/src/glbl.v")

    # IP
    if not os.path.isdir('axi_stream_lib'):
        os.system("vivado -mode tcl -source vivado_generate_ip.tcl")
        file_name = os.listdir("./")
        for file_i in file_name:
            if file_i.endswith('.jou') or file_i.endswith('.jou'):
                os.remove(file_i)

    # Libs
    lib = ui.add_library("osvvm_lib")
    lib.add_source_files(p.join(root_dir, 'libs', 'osvvm_lib', 'tags', '1.0.0', 'code', '*.vhd'))

    lib = ui.add_library("base_lib")
    lib.add_source_files(p.join(root_dir, 'libs', 'base_lib', 'tags', '1.1.0', 'code', '*.vhd'))

    lib = ui.add_library("sync_lib")
    lib.add_source_files(p.join(root_dir, 'libs', 'sync_lib', 'tags', '1.1.0', 'code', '*.vhd'))

    lib = ui.add_library("axi4_test")
    lib.add_source_files(p.join(root_dir, 'libs', 'axi4_test', 'tags', '1.0.0', 'code', '*.vhd'))

    lib = ui.add_library("check_lib")
    lib.add_source_files(p.join(root_dir, 'libs', 'check_lib', 'branches', 'trunk', 'code', '*.vhd'))

    ui.main()

[qarlosalberto]

Could you share the complete log? With --verbose

[Piressss]

Could you share the complete log? With --verbose

Compiling into sync_lib:          ..\..\..\..\sync_lib\tags\1.1.0\code\syncr_vector.vhd                                                failed
=== Command used: ===
C:\XilinxSysEd\Vivado\2017.4\bin\xvhdl.bat E:\svn\m200\libs\sync_lib\tags\1.1.0\code\syncr_vector.vhd -2008 -work sync_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\sync_lib -L vunit_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\vunit_lib -L axi_stream_lib_tb=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\axi_stream_lib_tb -L osvvm_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\osvvm_lib -L base_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\base_lib -L sync_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\sync_lib -L axi4_test=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\axi4_test -L check_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\check_lib -L axi_stream_lib=E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\axi_stream_lib

=== Command output: ===
ERROR: [XSIM 43-4316] Can not find file: E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\sync_lib

[qarlosalberto]

Could you have a previous error/warning with some file in the lib sync_lib and it isn't compiled? Is it the folder sync_lib empty?

[Piressss]

Could you have a previous error/warning with some file in the lib sync_lib and it isn't compiled? Is it the folder sync_lib empty?

syncr_vector.vhd is the first code being compiled, and the folder sync_lib is empty.

[Piressss]

What I see is that the compiler is not creating the folder sync_lib inside of folder vunit_out, instead is creating out of vunit_out, in the folder xsim.dir.

[qarlosalberto]

In E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\, are there more folders? Are they empty?

[Piressss]

In E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries, are there more folders? Are they empty?

Only vunit_out\xsim, the folder libraries was not created.

[qarlosalberto]

Can you try to run the example? https://github.com/softwareradiosystems/vunit/blob/xsim-rebase-v2/examples/vhdl/xsim-test/test.sh https://github.com/softwareradiosystems/vunit/tree/xsim-rebase-v2/examples/vhdl/xsim-test

[Piressss]

Can you try to run the example? https://github.com/softwareradiosystems/vunit/blob/xsim-rebase-v2/examples/vhdl/xsim-test/test.sh https://github.com/softwareradiosystems/vunit/tree/xsim-rebase-v2/examples/vhdl/xsim-test

PS C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\examples\vhdl\xsim-test> python .\mux_run.py tb_lib.mux_tb.10.Test_1

=============================================
xsim
=============================================
Compiling into vunit_lib: ..\..\..\vunit\vhdl\xsim\string_ops\src\string_ops.vhd        failed
=== Command used: ===
C:\XilinxSysEd\Vivado\2017.4\bin\xvhdl.bat C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\vunit\vhdl\xsim\string_ops\src\string_ops.vhd -2008 -work vunit_lib=C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\examples\vhdl\xsim-test\vunit_out\xsim\libraries\vunit_lib -L vunit_lib=C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\examples\vhdl\xsim-test\vunit_out\xsim\libraries\vunit_lib -L src_lib=C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\examples\vhdl\xsim-test\vunit_out\xsim\libraries\src_lib -L tb_lib=C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\examples\vhdl\xsim-test\vunit_out\xsim\libraries\tb_lib

=== Command output: ===
ERROR: [XSIM 43-4316] Can not find file: C:\Users\fepires\Downloads\vunit-xsim-rebase-v2\examples\vhdl\xsim-test\vunit_out\xsim\libraries\vunit_lib

For me some default config is forcing the Xsim to create the libraries in the wrong path.

[qarlosalberto]

It is really strange. I have not tested it on Windows, I use Linux: S

[Piressss]

I found what happended but not why.

The xvhdl command fails when I pass the directory to store the compiled files:

xvhdl.bat VHDL_FILE -2008 -work vunit_lib=MY_LIBRARY_PATH

However when let the Xsim determine the LIBRARY_PATH, I got success:

xvhdl.bat VHDL_FILE -2008 -work vunit_lib

[qarlosalberto]

I'm using Vivado 2018.4, can you test it with 2018.4? Does it fail if you run xvhdl manually with a vhdl file?

[Piressss]

Problem solved. I needed to generate the xsim.init with all libraries that must be compiled.

But now the problem is to use the XPM library, I have added this library to xsim.init but, the compiler are not understanding the "suffix context."

=== Command used: ===
C:\XilinxSysEd\Vivado\2017.4\bin\xvhdl.bat E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\axi_frame_decimation_tb.vhd -2008 -work axi_stream_lib_tb -initfile E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\xsim.init -L vunit_lib -L axi_stream_lib_tb -L osvvm_lib -L base_lib -L sync_lib -L axi4_test -L check_lib -L axi_stream_lib -L osvvm -L xpm

=== Command output: ===
INFO: [XSIM 43-3496] Using init file passed via -initfile option "E:\svn\m200\libs\axi_stream_lib\branches\trunk\simul\vunit_out\xsim\libraries\xsim.init".
INFO: [VRFC 10-163] Analyzing VHDL file "E:/svn/m200/libs/axi_stream_lib/branches/trunk/simul/axi_frame_decimation_tb.vhd" into library axi_stream_lib_tb
ERROR: [VRFC 10-1410] suffix vunit_context in the context reference does not denote a context declaration [E:/svn/m200/libs/axi_stream_lib/branches/trunk/simul/axi_frame_decimation_tb.vhd:9]
ERROR: [VRFC 10-149] 'vcomponents' is not compiled in library xpm [E:/svn/m200/libs/axi_stream_lib/branches/trunk/simul/axi_frame_decimation_tb.vhd:13]
INFO: [VRFC 10-307] analyzing entity axi_frame_decimation_tb
ERROR: [VRFC 10-1504] unit axi_frame_decimation_tb ignored due to previous errors [E:/svn/m200/libs/axi_stream_lib/branches/trunk/simul/axi_frame_decimation_tb.vhd:16]
INFO: [VRFC 10-240] VHDL file E:/svn/m200/libs/axi_stream_lib/branches/trunk/simul/axi_frame_decimation_tb.vhd ignored due to errors

[qarlosalberto]

Yes, context declaration is not supported by Xsim. You have to add the libraries manually:

library vunit_lib;
use vunit_lib.run_pkg.all;

[oholimoli]

hello what is the current progress on this issue? As far as I can read here XSIM seems to be partially supported. Will this feature be integrated here in the master branch?

[eine]

@oholimoli, see https://github.com/VUnit/vunit/issues/209#issuecomment-586913894 and https://github.com/VUnit/vunit/issues/209#issuecomment-335524828. It is unlikely to be integrated in the master branch, unless Vivado's VHDL support is improved to, at least, support the required VHDL 1993 features that VUnit uses. Still, @qarlosalberto has been doing a huge work to have the Python part used. You should check his fork.

[oholimoli]

@eine, thank you for your reply. I hope they will add support soon. Is there a free simulator available that allows using VUnit with a "Xilinx design" that comprises IP-cores, is written mainly in VHDL but has also some Verilog components (with some effort I could get rid of the Verilog part). Atm I use Modelsim.

[eine]

Unfortunately, AFAIK, there is no free and open source software that allows mixed-language simulation. I believe you can simulate a "Xilinx design" with GHDL, as long as you don't need any encrypted IP, and sources are VHDL only.

Moreover, it is possible to do mixed-language synthesis with GHDL and Yosys. The output of the synthesis can be simulated. Hence, it should be possible to do post-synthesis simulation of mixed-language designs with FOSS. However, this is a very experimental toolchain yet.

[qarlosalberto]

@Piressss I'm trying to simulate a fifo and I have a problem with glbl. Did you simulate it successfully?

[Piressss]

Did you mean glbl.v ?

If yes, I added the following at run.py and it works: xilinx_path = os.environ['XILINX_VIVADO'] xilinx_path = xilinx_path.replace("\\", "/") lib.add_source_file(xilinx_path + "/data/verilog/src/glbl.v"

I'm working on Windows 10.

[qarlosalberto]

Did you mean glbl.v ?

If yes, I added the following at run.py and it works: xilinx_path = os.environ['XILINX_VIVADO'] xilinx_path = xilinx_path.replace("\\", "/") lib.add_source_file(xilinx_path + "/data/verilog/src/glbl.v"

I'm working on Windows 10.

Thank you!

[qarlosalberto]

I have the same problem, I have added a simulation option in VUnit:

xilinx_path = os.environ['XILINX_VIVADO']
lib.add_source_file(xilinx_path + "/data/verilog/src/glbl.v")
ui.set_sim_option("xsim.enable_glbl", True)

[LarsAsplund]

@all I haven't been following this closely. What would you say are the most important things that Xilinx could do to improve on this? It used to be that there was no way to set the severity level at which the simulator stops. Is that still so? I'm looking for something specific (and simple) to feedback to https://forums.xilinx.com/t5/Simulation-and-Verification/Add-support-for-VUnit/td-p/1098552 and see if we can get some response from the Xilinx people.

[qarlosalberto]

@LarsAsplund I spent 2-3 weeks porting VUnit VHDL libraries to Xsim. It's impossible. The main problem is that XSim doesn't support variable access types. For example:

acc := new vav_t'(0 to acc'length + 2**16 => null);

I use VUnit with XSim daily. But I have created my own "VUnit libraries" with limited functionality:

https://github.com/softwareradiosystems/vunit/tree/xsim-rebase-v2/vunit/vhdl/xsim

I can simulate with VUnit+XSim mixed code, IPs, XPM... etc... But obviously I can't use BFMs and others nice features.

[imd1]

@LarsAsplund I spent 2-3 weeks porting VUnit VHDL libraries to Xsim. It's impossible. The main problem is that XSim doesn't support variable access types. For example:

acc := new vav_t'(0 to acc'length + 2**16 => null);

I use VUnit with XSim daily. But I have created my own "VUnit libraries" with limited functionality:

https://github.com/softwareradiosystems/vunit/tree/xsim-rebase-v2/vunit/vhdl/xsim

I can simulate with VUnit+XSim mixed code, IPs, XPM... etc... But obviously I can't use BFMs and others nice features.

I have used this version successfully - thanks for the update.

However I have come across a couple of issues:

• there is no test_runner_watchdog VHDL procedure implemented. Was this omitted because it was not needed or is it difficult to implement?
• the code contains a couple of bugs in the main Vunit code as the baseline was taken between 4.2.0 and 4.3.0 and a fix was added to 4.3.0. Is it a straightforward process to update this repo from the main Vunit repo (rebase?)

[qarlosalberto]

• I think that there is no problem to add test_runner_watchdog.

• I plan to rebase the man VUnit repo, but I need to refactor my code. I will do it when I have more time.

[arnfol]

I've tried to run this fork inside a Win10 WSL with Vivado 2018.3, and got some problems. It looks like something went wrong with a compilation order inside the Vivado:

log

``` ****** Vivado v2018.3 (64-bit) **** SW Build 2405991 on Thu Dec 6 23:36:41 MST 2018 **** IP Build 2404404 on Fri Dec 7 01:43:56 MST 2018 ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved. source /mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vivado/tcl/extract_compile_order.tcl -notrace Scanning sources... Finished scanning sources INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2018.3/data/ip'. INFO: [IP_Flow 19-1686] Generating 'Synthesis' target for IP 'fifo_8b_32w'... INFO: [IP_Flow 19-1686] Generating 'Simulation' target for IP 'fifo_8b_32w'... INFO: [Common 17-206] Exiting Vivado at Wed Nov 11 12:46:03 2020... Compiling into vunit_lib: ../../../vunit/vhdl/xsim/string_ops/src/string_ops.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/string_ops/src/string_ops.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/run/src/run_types.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/run/src/run_types.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/logging/src/logger_pkg.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/logging/src/logger_pkg.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/logging/src/logger_pkg_body.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/logging/src/logger_pkg_body.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/dictionary/src/dictionary.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/dictionary/src/dictionary.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/data_types/src/types.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/data_types/src/types.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/run/src/run_api.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/run/src/run_api.vhd" into library vunit_lib WARNING: [VRFC 10-2115] shared variables must be of a protected type [/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/run/src/run_api.vhd:19] Compiling into vunit_lib: ../../../vunit/vhdl/xsim/data_types/src/integer_array_pkg.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/data_types/src/integer_array_pkg.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/core/src/stop_pkg.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/core/src/stop_pkg.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/core/src/stop_body_2008p.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/core/src/stop_body_2008p.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/core/src/core_pkg.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/core/src/core_pkg.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/run/src/run.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/run/src/run.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/check/src/check_api.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/check/src/check_api.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/xsim/check/src/check.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/xsim/check/src/check.vhd" into library vunit_lib Compiling into vunit_lib: ../../../vunit/vhdl/vunit_context_xsim.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/vunit/vhdl/vunit_context_xsim.vhd" into library vunit_lib Compiling into lib: src/top.vhd passed WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/top.vhd" into library lib INFO: [VRFC 10-3107] analyzing entity 'top' Compiling into tb_lib: src/test/tb_top.vhd failed === Command used: === /opt/Xilinx/Vivado/2018.3/bin/xvhdl /mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd -2008 -work tb_lib=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vunit_out/xsim/libraries/tb_lib -L vunit_lib=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vunit_out/xsim/libraries/vunit_lib -L lib=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vunit_out/xsim/libraries/lib -L tb_lib=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vunit_out/xsim/libraries/tb_lib -L unisim=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vivado_libs/standard/unisim -L unimacro=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vivado_libs/standard/unimacro -L unifast=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vivado_libs/standard/unifast -L secureip=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vivado_libs/standard/secureip -L xpm=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vivado_libs/standard/xpm -L fifo_generator_v13_2_3=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vunit_out/xsim/libraries/fifo_generator_v13_2_3 -L xil_defaultlib=/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/vunit_out/xsim/libraries/xil_defaultlib === Command output: === WARNING: [XSIM 43-3479] Unable to increase the current process stack size. INFO: [VRFC 10-163] Analyzing VHDL file "/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd" into library tb_lib INFO: [VRFC 10-3107] analyzing entity 'tb_top' ERROR: [VRFC 10-2989] 'info' is not declared [/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd:51] ERROR: [VRFC 10-2989] 'info' is not declared [/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd:64] ERROR: [VRFC 10-2989] 'check_equal' is not declared [/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd:68] ERROR: [VRFC 10-2989] 'test_runner_watchdog' is not declared [/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd:86] ERROR: [VRFC 10-3782] unit 'tb' ignored due to previous errors [/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd:20] INFO: [VRFC 10-3070] VHDL file '/mnt/c/Users/arnfo/Work/vunit_xsim/examples/vhdl/vivado/src/test/tb_top.vhd' ignored due to errors Compile failed ```

In the example I also faced a problem with the examples\vhdl\vivado\tcl\compile_standard_libs.tcl: compile_simlib's argument -32bit does not work on my 64-bit system) So I just get rid of it.

[imd1]

Yes, you have found the missing test_runner_watchdog issue I found plus other missing features - you must refactor your code to avoid them or wait for a fix

[qarlosalberto]

@imd1 I have updated the code to the las VUnit version in this branch: https://github.com/softwareradiosystems/vunit/tree/xsim_support

[fcaruso-PL]

@qarlosalberto what version of vivado does it require? When I run 2020.2 the verilog tests in verbose mode but the summary does not report any failed tests. Do I need any specific settings beside xport VUNIT_XSIM_PATH=<...>/Vivado/2020.2/bin/ ? Thanks!

[qarlosalberto]

Sorry, I haven't test it with Verilog. Only with VHDL.

[fcaruso-PL]

I am having problems with the mif files. When I run vunit/xsim it doesn't find the Memory Initialization Files of the external IPs. Is there a workaround beside patching up the verilog files with the absolute address of the mif?

[LudvigVidlid]

@qarlosalberto , I've created a pull request to your fork, adding an xelab_flags simulation option for xsim.

I realize that the fork is a year behind, so I could make the effort to bring it up-to-date if anyone would benefit from it :)

[qarlosalberto]

Cool, thanks!

I'm working with an internal branch, I need to merge my changes and later I could add the xelab_flags. It would nice to bring it up-to-date the branch, I know some developers use it a lot.

[qarlosalberto]

I have updated the branch, it includes:

xsim:
  Xsim specific flags

  --xsim-vcd-path XSIM_VCD_PATH
                        VCD waveform output path.
  --xsim-vcd-enable     Enable VCD waveform generation.
  --xsim-xelab-limit    Limit the xelab current processes to 1 thread.

And xsim.xelab_flags added by @LudvigVidlid

[LudvigVidlid]

Thanks for merging, @qarlosalberto :)

I've attempted to bring xsim_support up-to-date with vunit, pr here. It works with my tests, which are only using xsim and SystemVerilog. Do you have a chance to try it with your use cases?

[LarsAsplund]

@LudvigVidlid @qarlosalberto Do you have a list of missing VHDL support in latest XSIM (2022.1). Have there been any relevant improvements? I have a person within Xilinx that I hope can bring our issues to the right people so I'd like current status from those having some experiences in this area.

[kmtaylor]

I've been working on getting 2022.1 working. Adding to qarlosalberto's work, I've been able to get the com library going as well as the axi stream modules. Generally it's been a process of swapping the linked lists in com to fixed size arrays. Ugly but works. If you want to take a look, my fork is here: https://github.com/kmtaylor/vunit/tree/kimt/xsim_support

[antho24]

I have created a fork from the master branch here: https://github.com/antho24/vunit

I have pull in changes from qarlosalberto and kmtaylor latest work and merged with the master branch on VUnit/vunit. I also added support for running sim with verilog/systemverilog testbenches, including UVM (I have mainly tested with UVM testbench on Windows platform).

Outstanding issue for my fork is all related to VHDL testbench. I couldn't run a successful VHDL testbench yet due to xsim elaboration failure on this specific error: [VRFC 10-932] initial value for constant declaration is not constant. Seem related to using impure function to set value for constant.

Another problem is with using multiple generic value. I couldn't get subprocess to correctly parse testbench that have multiple generic parameters being set. If someone can help me fix that, it would be much appreciated.

[qarlosalberto]

@antho24 I think that I know your problem with the generics. I have solved it creating a SV testbench wrapper.

[kmtaylor]

Hi @antho24 - I had that error (initial value for constant declaration is not constant) a lot. It appears to be a bug in xsim. In many cases I could fix it by swapping constants for integer literals like this:

https://github.com/kmtaylor/vunit/blob/kimt/xsim_support/vunit/vhdl/xsim/data_types/src/queue_pkg-body.vhd#L21

I also noticed on your branch that you've altered builins.py to use the full libraries. I'm afraid you won't have much luck with this, as 2022.1 is still missing many features and is quite buggy.

[LudvigVidlid]

Outstanding issue for my fork is all related to VHDL testbench. I couldn't run a successful VHDL testbench yet due to xsim elaboration failure on this specific error: [VRFC 10-932] initial value for constant declaration is not constant. Seem related to using impure function to set value for constant.

@antho24 I think we had a similar problem with another simulator. We solved it by making a deferred constant (i.e. declaring the constant in the package header, and defining it in the package body). I'm not sure if that is applicable to your case?

[LudvigVidlid]

Another problem is with using multiple generic value. I couldn't get subprocess to correctly parse testbench that have multiple generic parameters being set. If someone can help me fix that, it would be much appreciated.

@antho24 This sounds familiar as well. We had issues getting xsim to work on command line on windows, and now do it differently between linux and windows. Maybe this would work for you?

[LarsAsplund]

Vivado 2022.2 claim VHDL 2008 support in the release notes. Have anyone tested if that makes a difference?