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VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
http://vunit.github.io/
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SystemVerilog support #294

Closed alinaivanovaoff closed 6 years ago

alinaivanovaoff commented 6 years ago

Hi!

Could you clarify, please, what part of SystemVerilog is supported by VUnit or where I can check it? My company uses SystemVerilog and we worry what we cannot use VUnit because of it.

Best regards, Alina Ivanova

LarsAsplund commented 6 years ago

As long as the simulator is supported by VUnit and the testbench is on the format described here you can use VUnit. What parts of SystemVerilog you can use to describe the rest of your testbench depends on what your simulator supports.

For VHDL we also provide a number of support packages which we don't for SystemVerilog. However, many of the features in those packages are things already supported by SystemVerilog.

alinaivanovaoff commented 6 years ago

Thanks for quick answer. I just confused about "SystemVerilog (Support is experimental)"

LarsAsplund commented 6 years ago

The reason for "experimental" is that the main developers do not use SystemVerilog professionally so we have limit personal experiences. We, like most of the VUnit community, use VHDL but there are also SystemVerilog users out there and we haven't had many complaints. The Python part of VUnit which is responsible for handling the simulator is mostly HDL language independent. It doesn't care about what language is driving the simulation. So most of the things used to drive a SystemVerilog testbench is also used when using VUnit with VHDL.

If you're willing to give it a try we would be happy to take any feedback you may have. You can use this forum or our chat.

LarsAsplund commented 6 years ago

@alinaivanovaoff I'm closing this issue now but you may also be interested in the work to add VUnit support for the free Icarus Verilog simulator. For more information see #188.