parser gives no indication of the error

[asicnet]

Hi I get a error and can not find the reason.

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E:/VUnit/vunit\vunit Traceback (most recent call last): File "ctrl_system\vunit\run.py", line 39, in

*lib.add_source_files( join ( project_path, dirName, module , "src", "vhdl", ".vhd" ) )**

File "E:/VUnit/vunit\vunit\ui.py", line 1149, in add_source_files for file_name in file_names]) File "E:/VUnit/vunit\vunit\ui.py", line 1149, in for file_name in file_names]) File "E:/VUnit/vunit\vunit\ui.py", line 1192, in add_source_file no_parse=no_parse) File "E:/VUnit/vunit\vunit\project.py", line 126, in add_source_file no_parse=no_parse) File "E:/VUnit/vunit\vunit\project.py", line 818, in init design_file = vhdl_parser.parse(self.name) File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 37, in parse database=self._database) File "E:/VUnit/vunit\vunit\cached.py", line 45, in cached result = function(content) File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 68, in parse return cls(entities=list(VHDLEntity.find(code)), File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 325, in find yield VHDLEntity.parse(sub_code[:match.end()]) File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 345, in parse ports = cls._find_port_clause(code) File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 397, in _find_port_clause code[match.start(): match.end() + closing_pos + match_semicolon.end()]) File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 474, in _parse_port_clause port_list.append(VHDLInterfaceElement.parse(interface_element, is_signal=True)) File "E:/VUnit/vunit\vunit\vhdl_parser.py", line 574, in parse mode_split = interface_element_string.split(':')[1].strip().split(None, 1) IndexError: list index out of range

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The directory has many files and the search for the error was very long. The vcom command outsite of vunit showed the problem!

The error was

entity xy is port ( a :in std_logic; ....... last : out stdlogic **;_**

); end entity;

This last ';' in the lat line was the reason. Missing ";" is no Problem.

Maybe the vunit parser can show the file or better the line within the file.

see you Helmut

[joshrsmith]

I have had this happen to me a few times as well and it is annoying to track down. If nothing else, I agree that simply printing out the file in which the parse error occurred could be helpful.

[kraigher]

This is a regression on previous functionality from a refactoring. The code used to print the file name and recover from the error such that the source file would eventually be compiled.

[asicnet]

Sorry, but i don't understand. The vunit parser check the file for some informations. It see that a mistake is within the file, so it can say the the fiele is not correct. The source file is not compiled. Here I would see a vcom compiler error. Too bad that no action is needed here for you

see you Helmut

[kraigher]

What do you mean exactly? The way it works now after my fix is that when the parsers stumbles upon illegal VHDL it will:

1. print the Python traceback
2. print the name of the file
3. continue compiling files including the one which caused a parse failure.

This behavior was the intention but was lost in a referactoring. I added a test for it now to avoid this happening in the future.

The behavior before my fix was to stop after step 1. above not do anything more.

[kraigher]

Unless you did not see it. I closed this issue from the commit that fixed the issue. So the problem should be solved on master.

[asicnet]

I did not understand the comment, so thank you 👍

[asicnet]

I test it!! Very good, Thanks and see you Helmut