Adding vunit_pkg for both VHDL and SytemVerilog

[LudvigVidlid]

We'd like to allow both SystemVerilog and VHDL test benches in our project. From #297 I learned that

from vunit import VUnit

should be used for VHDL, and

from vunit.verilog import VUnit

should be used for SystemVerilog.

Basically, I want to add both versions of vhdl_pkg, which I now do in this way:

from vunit import VUnit
## I omit a lot of code here..
# Create VUnit instance from custom arguments
vu = VUnit.from_args(args=args)
# Add vunit_pkg for SystemVerilog form the function in builtins.py
vu._builtins.add_verilog_builtins()

This does what I want - the VHDL and SystemVerilog files both use the vhdl_pkg type I'd like them to.

Three questions: A) I fear that I am simply lucky that my simulator (QuestaSim) uses the files I want it to. Do you know upfront if this could be the case? B) Is there already a better way to do this? C) If you think that (A) is no problem, I could make a pull request with a new VUnit class similar to that of the verilog-VUnit class:

#File name e.g. mixed_hdl.py
class VUnit(VUnitVHDL):
    """
    VUnit VHDL and Verilog mixed simulation interface
    """

    def add_builtins(self):  # pylint: disable=arguments-differ
        """
        Add vunit VHDL and Verilog builtin libraries
        """
        self._builtins.add_vhdl_builtins()
        self._builtins.add_verilog_builtins()

Thanks! /Ludde

[kraigher]

The solution you already have (to explicitly add the verilog builtins) should work. If you want you can add a mixed class which does this out of the box if you think it is more convenient. The only thing that differ between these classes are what files are automatically added to the project.