Closed joshrsmith closed 9 years ago
@joshrsmith I can reproduce the problem and it is not simulator specific.
The VUnit parser converts everything to lower case since VHDL is not case sensitive. Thus a Data_width generic is called data_width by VUnit internally. The add_config and set_generic methods of the VUnit Python class however does not transform the generic name provided by the user into lower case when checking against the internal representation causing the problem. If you would reference the generic as entirely lower case in your run.py
file you could work around the problem.
I will fix this right away and make a new release.
The work-around you suggested worked for me.
A fix would be appreciated in order to avoid this issue in the future--I thought I was losing my mind with an example nearly identical to the one provided with vunit.
I will push a fix just about any minute now. I also added a warning message when the user specifies a generic that is not present in the entity so that would have triggered in this case and made the VUnit bug easier to locate.
Fixed and released in v0.38.0. Thank you for reporting it.
I confirm as fixed.
I am using Riviera/Active HDL. Not sure if this affects other simulators.
When generating testcases for a testbench by assigning generic values, if the generic has capitals in it, the generic will not be assigned to the simulation successfully.
For example, if the "generate_tests" example is modified such that:
and the run.py is updated accordingly, the simulator will complain that "No value assigned to generic/parameter "Data_width""
When looking at the batch files generated for running the simulation, it appears that the generics are not present in there, either:
I am guessing this is some edge case related to case-sensitivity in VHDL.