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VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
http://vunit.github.io/
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Question: Running tcl scripts from VHDL files #959

Closed nselvara closed 8 months ago

nselvara commented 9 months ago

Hi guys, thanks a lot for this open source project. I really like it and use it very often. Regarding the actual question, is it actually possible to run a tcl script from a VHDL file? This would help me to reduce the simulation time significantly (75 %). The use case is actually to fill up a RAM-IP block provided by Intel (altera_mf). Unfortunately, VHDL currently doesn't allow to force variables from a process to a certain state. Hence, there are 2 options either wait out the dead time or ModelSim provides the feature to force a variable via tcl script. Thank you for any hint and wish you a nice weekend.

oscargus commented 9 months ago

I'm not sure this is what you are looking for, but I often solve what appears to be a similar problem by adding another port to the memory. In that way, the test bench can write everything "instantly". This is naturally not possible to synthesize or anything and depending on where the memory is in the hierarchy may provide more or less overhead.

Now, you mention that you have an IP-block, so then it won't work (easily), but maybe it is possible to swap these blocks?

Either way: I'd suggest https://electronics.stackexchange.com/ and/or https://www.edaboard.com/ as probably better alternatives for this type of questions not directly related to vunit.