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VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog
http://vunit.github.io/
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Feature: axi master implementation #960

Open DavidMartinPhios opened 9 months ago

DavidMartinPhios commented 9 months ago

Hi guys,

thank you for the open source project. We are using the project in several of our projects and we are really satisfied with it. We are also heavily using the verification components especially in combination with AXI interfaces.

What we are missing is a full axi master verification component. Is there a plan from your side to implement this component or is there a special reason why you are not implement it?

If this feature is not planned from your side we would really like to support the implementation of this feature with our development team and would be pleased to get in direct contact for discussion.

Thank you.

joshrsmith commented 9 months ago

FWIW, people I work with would also be very interested in a component like this. We have hacked together streaming VCs to achieve an "AXI Master" in the past, but it's not the same as having a true AXI Master VC.

You have my vote that this would be useful.

CodablePanda commented 7 months ago

I'm also interested and would be happy to help out with this. I have been looking at the boards and see that some comments indicate that there is progress in rewriting the verification components (#726 and #480 for example). I couldn't find the repository where this work is happening though. Is there an update on the status of the verification components and is there a way for me to contribute?

DavidMartinPhios commented 1 month ago

Hi, after a longer break from my side i would like to start with the implementation of the axi master verification component. Are there any updates related to this component or to any other rewriting progress?