Fix regex for VHDL component instantiations - Githubissues

VUnit / vunit

VUnit is a unit testing framework for VHDL/SystemVerilog

http://vunit.github.io/

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Fix regex for VHDL component instantiations #990

Open javValverde opened 4 months ago

javValverde commented 4 months ago

Add comments to the multiline regex
Extend unittest for vhdl_parser