nv_small FPGA Mapping Workflow - Max's Blog

[VVViy]

https://vvviy.github.io/2018/09/12/nv_small-FPGA-Mapping-Workflow-I/

Keep self busy.

[VVViy]

Comment Test

[honorpeter]

谢谢，厉害!

[VVViy]

@peterzh2018 谢谢，厉害!

:handshake:

[ghost]

兄弟在哪里工作？有没有qq可以加上，建议建个群大家一起讨论，我的qq号是348277646，能加下吗，谢谢

[VVViy]

@peterzh2018888 兄弟在哪里工作？有没有qq可以加上，建议建个群大家一起讨论，我的qq号是348277646，能加下吗，谢谢

不好意思啊，周末在家不google，qq已加。

确实没考虑过建群，因为对于工程实现，肯定还是官网issue的参与度更高，而对于源码分析，这是个体力活，愿意分享且真正能讨论出东西的人并不容易遇见，所以没考虑过，另外，也是因为手头一直比较忙碌。

[ghost]

再按

@VVViy Step 2: Create RTL Project (Win10) 3.关闭clock gating，原设计对RAM存储op使用了大量clock gating以降低功耗，但与processor，ASIC不同，FPGA的时钟树是设计好的，clock buf资源有限，若不关闭gating，可能产生很大skew(之前因为部分gating未关闭，测试一直不过). 使用到的clock gating开关宏包括以下4个，有4种设置方式：i）在vivado的Project Settings->General->Verilog options->Defines中添加宏名称和值 请问：宏值是多少，是写0还是1 IP生成以后添加到应用的BD工程，这些宏定义是不是在新的工程里还需要再按同样方法进行设置？

[VVViy]

@peterzh2018888 再按

@VVViy Step 2: Create RTL Project (Win10) 3.关闭clock gating，原设计对RAM存储op使用了大量clock gating以降低功耗，但与processor，ASIC不同，FPGA的时钟树是设计好的，clock buf资源有限，若不关闭gating，可能产生很大skew(之前因为部分gating未关闭，测试一直不过). 使用到的clock gating开关宏包括以下4个，有4种设置方式：i）在vivado的Project Settings->General->Verilog options->Defines中添加宏名称和值 请问：宏值是多少，是写0还是1 IP生成以后添加到应用的BD工程，这些宏定义是不是在新的工程里还需要再按同样方法进行设置？

最稳妥的方式是最后一种的笨方法，前三种是别人测试过，我没测过； 宏值？加不加都无所谓； 不是，是在package ip前做，在BD里不需要。

您原来的工作内容是？

[VVViy]

@peterzh2018

@peterzh2018888 再按 @VVViy Step 2: Create RTL Project (Win10) 3.关闭clock gating，原设计对RAM存储op使用了大量clock gating以降低功耗，但与processor，ASIC不同，FPGA的时钟树是设计好的，clock buf资源有限，若不关闭gating，可能产生很大skew(之前因为部分gating未关闭，测试一直不过). 使用到的clock gating开关宏包括以下4个，有4种设置方式：i）在vivado的Project Settings->General->Verilog options->Defines中添加宏名称和值 请问：宏值是多少，是写0还是1 IP生成以后添加到应用的BD工程，这些宏定义是不是在新的工程里还需要再按同样方法进行设置？

最稳妥的方式是最后一种的笨方法，前三种是别人测试过，我没测过； 宏值？加不加都无所谓； 不是，是在package ip前做，在BD里不需要。

您原来的工作内容是？

确实是第三种比较可靠，前几种好像Pakage IP 时警告说不能保持那个头文件的global属性。

好的。

我以前是做电路设计的。

还有个问题想问下您，我是按照您写的把CSB 总线 APB 和DBB 总线 AXI在一个IP里了，这样在设备树PL。stsi里只能看到一个IP的interruput，地址啥的就是APB的，这样是不是没法用nvdla的AXI口或其中断了？

电路设计？板级还是片级？是前端吗？ 上面博客中的最后一副图已经描述了AXI, APB, INTR接口的连接了，你问的内容是device tree中node的相关属性，一句两句解释不清，你要真想了解就去找我写的另一篇博客和相关参考资料吧。

[VVViy]

不必客气，老师不敢当，只是从导师那里学了些皮毛，架构设计的路还很长。

[ghost]

@vvviy 您是博士?哪个学校的?现在还没毕业吗？

[VVViy]

@peterzh2018888 @vvviy 您是博士?哪个学校的?现在还没毕业吗？

嗯，北理17年毕业的。

[honorpeter]

@peterzh2018888 @VVViy 您是博士?哪个学校的?现在还没毕业吗？

嗯，北理17年毕业的。

@VVViy Thank you very much ,I had succeed with you kind help. Test all had passed include NN. By the way， there is an issuse https://github.com/nvdla/hw/issues/183#issue-344342801
Whether it needs to be handled？

[VVViy]

@honorpeter

@peterzh2018888 @VVViy 您是博士?哪个学校的?现在还没毕业吗？

嗯，北理17年毕业的。

@VVViy Thank you very much ,I had succeed with you kind help. Test all had passed include NN. By the way， there is an issuse https://github.com/nvdla/hw/issues/183#issue-344342801
Whether it needs to be handled？

Actually, if VLIB_BYPASS_POWER_CG macro is well defined, then gating clock “nvdla_core_gated_clk” will be switched off. As such, "nvdla_core_ng_clk" equal to "nvdla_core_clk" signal. u can trace NV_NVDLA_cdma.v, NV_NVDLA_CDMA_wt.v, NV_NVDLA_CDMA_slcg.v, and NV_CLK_gate_power.v to check.

BTW, a little advice, more patience and attenion u have, more interesting thing u will get. Good luck!

[honorpeter]

@honorpeter

@peterzh2018888 @VVViy 您是博士?哪个学校的?现在还没毕业吗？

嗯，北理17年毕业的。

@VVViy Thank you very much ,I had succeed with you kind help. Test all had passed include NN. By the way， there is an issuse nvdla/hw#183 (comment) Whether it needs to be handled？

Actually, if VLIB_BYPASS_POWER_CG macro is well defined, then gating clock “nvdla_core_gated_clk” will be switched off. As such, "nvdla_core_ng_clk" equal to "nvdla_core_clk" signal. u can trace NV_NVDLA_cdma.v, NV_NVDLA_CDMA_wt.v, NV_NVDLA_CDMA_slcg.v, and NV_CLK_gate_power.v to check.

BTW, a little advice, more patience and attenion u have, more interesting thing u will get. Good luck!

Thank you for your patience and attenion, good advice.

[gitosu67]

Should I set NV_nvdla as the top file before clicking on 'Create and Package new IP' ?

[VVViy]

@Okaymaddy Should I set NV_nvdla as the top file before clicking on 'Create and Package new IP' ?

Actually, no, you have to create a new wrapper file, like NV_NVDLA_wrapper.v, and add NV_nvdla and NV_NVDLA_apb2csb instances to it. This wrapper file is right TOP file. After that, you need connect pin/port signals, and append lost AXI signals to apply AXI interconnect/Xilinx smartconnect in BD project. You can follow Step 3.

[gitosu67]

I tried creating the wrapper of NV_nvdla and NV_NVDLA_ap2csb as you mentioned in the comments. Then I synthesized the design but I am getting an error 'Module DW_02_multp not found' and also 'failed in synthesizing module NV_NVDLA_CMAC_CORE_mac'. Any suggestions on how to fix these errors?

[VVViy]

@Okaymaddy I tried creating the wrapper of NV_nvdla and NV_NVDLA_ap2csb as you mentioned in the comments. Then I synthesized the design but I am getting an error 'Module DW_02_multp not found' and also 'failed in synthesizing module NV_NVDLA_CMAC_CORE_mac'. Any suggestions on how to fix these errors?

1) "Module DW_02_MULTP not found", when u setup tree.make , u have to type '0' for "Enter to determine designware_noexist". Or u can add DESIGNWARE_NOEXIST macro to your built vmod. 2) 'failed in synthesizing module NV_NVDLA_CMAC_CORE_mac', for such limited infomation, i have no idea why this happened.

[gitosu67]

@VVViy I am getting this error while I am trying to package the wrapper IP: https://prnt.sc/o04bhi. Any ideas why this is happening?

[VVViy]

@Okaymaddy @VVViy I am getting this error while I am trying to package the wrapper IP: https://prnt.sc/o04bhi. Any ideas why this is happening?

From the reported error, some AXI required signals(ports) is lost. So, u need to 1) add all of AXI signals absent in original nvdla vmod to NV_nvdla pin signal list and top wrapper port signal list according to AXI SPEC(AMBA® AXI™ and ACE™ Protocol Spec AXI3,4 ACE) 2) assign approciate value to these signals 3) select all of AXI signals to declare AXI interface before package ip

[gitosu67]

@VVViy I was able to create the wrapper and run synthesis but I am getting the following error on implementation:

I am using the xczu9eg-ffvb1156-1LV-i board for synthesis and implementation (This has 668 available IOBs). I could not find any other device of the ZynUltrascale+ family with higher available IO pins. Any suggestions on how to fix this will be fo great help!

[VVViy]

@Okaymaddy @VVViy I was able to create the wrapper and run synthesis but I am getting the following error on implementation:

I am using the board for synthesis and implementation (This has 668 available IOBs). I could not find any other device of the ZynUltrascale+ family with higher available IO pins. Any suggestions on how to fix this will be fo great help!

Uh....., actually, u can not sythsize and implement the source code in PL part of xczu9eg-ffvb1156-1LV-i, because of nvdla has LARGE scale IOB requirements(mainly AXI). You have to package nvdla ip and in block design enviroment connect all AXI, APB and other signals to ARM core inside chip to save FPGA IO pins.

[gitosu67]

@VVViy Yes I created the NVDLA wrapper, connected it with AXI, APB and other signals in the block design environment. (According to figure 5 in your blog). Now I run synthesis after all the connections are made and it passes correctly. The issue is when I run implementation I get the error as I have shown in my previous comment. Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?

[VVViy]

@Okaymaddy @VVViy Yes I created the NVDLA wrapper, connected it with AXI, APB and other signals in the block design environment. (According to figure 5 in your blog). Now I run synthesis after all the connections are made and it passes correctly. The issue is when I run implementation I get the error as I have shown in my previous comment. Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?

You mean u got the previous errors, when u implement the block design project? That's wired. I have never heard of this. Your block design is as same as above fig-5? What in your implement xdc file?

[gitosu67]

I was able to correct the previous error but now I am getting this critical warning after running Synthesis:

I get this as an error while running Implementation.

I am running Out of context per IP. Is there any way you can help to get rid of this error? As for the xdc file I am not sure how to check implement xdc, but I have added the two xdc files as you have said in your blog. Any suggestions will be really helpful!

[VVViy]

@Okaymaddy I was able to correct the previous error but now I am getting this critical warning after running Synthesis:

I get this as an error while running Implementation.

I am running Out of context per IP. Is there any way you can help to get rid of this error? As for the xdc file I am not sure how to check implement xdc, but I have added the two xdc files as you have said in your blog. Any suggestions will be really helpful!

NV_BLKBOX_SINK? This is because u didn't switch off the NV_BLKBOX_SINK instances by using FPGA macro. I advise u manully add head file including all of required macros into every needed source files, this may be a stupid method, but it works.

[gitosu67]

Hi, I set the FPGA macro in some of the relevant files, I also put it in global includes.

But, I am still getting the same error. Am I missing something here? Any help will be really appreciated!

[VVViy]

@Okaymaddy Hi, I set the FPGA macro in some of the relevant files, I also put it in global includes.

But, I am still getting the same error. Am I missing something here? Any help will be really appreciated!

You should try to mannually put the macro.vh file into the files, but not set it as global includes, am i making sense?

[gitosu67]

Yes, that helped and I made the changes. Now during Bitstream generation, I am getting an error that IOSTANDARD is not set for some pins. So I looked it up and used the command:

_set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks -filter { BANK_TYPE !~ "BTMGT" }]]

in the tcl console. This will set all non-MGT pins to an IOSTANDARD (in this case LVCMOS18): Is this correct to do?

[VVViy]

@Okaymaddy Yes, that helped and I made the changes. Now during Bitstream generation, I am getting an error that IOSTANDARD is not set for some pins. So I looked it up and used the command:

_set_property IOSTANDARD LVCMOS18 [get_ports -of_objects [get_iobanks -filter { BANK_TYPE !~ "BTMGT" }]]

in the tcl console. This will set all non-MGT pins to an IOSTANDARD (in this case LVCMOS18): Is this correct to do?

As you see, in above Fig-5, there is no need to connect external port. So, i did not set pin constraints. If u have, u just manually or automatic set pin attributes in xdc file.

[gitosu67]

Sorry I have a stupid question. While packaging the NVDLA IP, do we need to make any changes in the 'File groups'?

If I try to select all the files from there I get an error 'NV_NVDLA is not found' while generating the output products. But if I don't select anything there is no error. So do I leave everything unselected in File groups?

[VVViy]

@Okaymaddy Sorry I have a stupid question. While packaging the NVDLA IP, do we need to make any changes in the 'File groups'?

If I try to select all the files from there I get an error 'NV_NVDLA is not found' while generating the output products. But if I don't select anything there is no error. So do I leave everything unselected in File groups?

Select files in 'File Groups'? How to do it? I did not remember there is some special treatment.

[saikat007]

Hi, @VVViy Which fifo files are you including in your project? ( I am using the files from hw/vmod/fifos. Not sure if that is correct! ) Also are you using ALL the files from outdir/nv_small/vmod/nvdla?

[VVViy]

@saikat007 Hi, @VVViy Which fifo files are you including in your project? ( I am using the files from hw/vmod/fifos. Not sure if that is correct! ) Also are you using ALL the files from outdir/nv_small/vmod/nvdla?

I worked on nv_small branch, so there was no need to select fifos. For small version, not all files were used.

[saikat007]

@VVViy If I don't give any fifo files, I run across errors like these:

How to fix this?

[VVViy]

@saikat007 @VVViy If I don't give any fifo files, I run across errors like these:

How to fix this?

Yeah, it seems that new update of nvdlav1 branch, or nv_small branch (i don't remember) need to select fifo files from that directory. In my opinion, you can select required fifos according to reported errors, like NV_NVDLA_CDP_RDMA_lat_fifo_65x8.v.

[saikat007]

Hi @VVViy How do you properly customize the Zynq IP block(as shown below) to be able to run on fpga?

[VVViy]

@saikat007 Hi @VVViy How do you properly customize the Zynq IP block(as shown below) to be able to run on fpga?

Except APU block, perhas, other subsystems are default setup, such detailed question it's really hard to anwser, too long time.

[Rubick-fafafa]

@VVViy 你好 请问step3是要自己新建一个NV_nvdla_wrapper.v然后在里面例化NV_nvdla和NV_NVDLA_apb2csb吗?

[VVViy]

@Rubick-fafafa @VVViy 你好 请问step3是要自己新建一个NV_nvdla_wrapper.v然后在里面例化NV_nvdla和NV_NVDLA_apb2csb吗?

是的

[pross0123]

你好，请问能再详细讲讲wrapper该怎么写吗。还是不太明白。谢谢

[pross0123]

@Okaymaddy @VVViy I am getting this error while I am trying to package the wrapper IP: https://prnt.sc/o04bhi. Any ideas why this is happening?

Hi, Have you solved this problem? I am facing the same problem

[LeiWang1999]

@pross0123 Hi Given my preceding research, the NVDLA version of this tutorial is out of date, you can dive into my new post: https://leiblog.wang/NVDLA-Xilinx-FPGA-Mapping/

[LeiWang1999]

@pross0123 And Github Page is https://github.com/LeiWang1999/ZYNQ-NVDLA I had putted all code here.

[VVViy]

@pross0123 你好，请问能再详细讲讲wrapper该怎么写吗。还是不太明白。谢谢

年后梯子一直不稳，一直没上来了，不好意思啊。NVDLA已经是几年前的一个版本工作了，blog里有些细节对于新版本不可用了，可以参考楼上人的工作。

[sunny-yellow]

@Okaymaddy @VVViy Yes I created the NVDLA wrapper, connected it with AXI, APB and other signals in the block design environment. (According to figure 5 in your blog). Now I run synthesis after all the connections are made and it passes correctly. The issue is when I run implementation I get the error as I have shown in my previous comment. Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?

Hello, could you tell me how do you fix the problem?

[VVViy]

@sunny-yellow

@Okaymaddy @VVViy Yes I created the NVDLA wrapper, connected it with AXI, APB and other signals in the block design environment. (According to figure 5 in your blog). Now I run synthesis after all the connections are made and it passes correctly. The issue is when I run implementation I get the error as I have shown in my previous comment. Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?

Hello, could you tell me how do you fix the problem?

What problem? About "Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?" ? Yes

[sunny-yellow]

yes, it's the problem as you said, and I resolved it. Thank you.

------------------ 原始邮件 ------------------ 发件人: "VVViy/VVViy.github.io" @.>; 发送时间: 2021年9月18日(星期六) 晚上7:41 @.>; @.**@.>; 主题: Re: [VVViy/VVViy.github.io] nv_small FPGA Mapping Workflow - Max's Blog (#4)

@sunny-yellow

@Okaymaddy @VVViy Yes I created the NVDLA wrapper, connected it with AXI, APB and other signals in the block design environment. (According to figure 5 in your blog). Now I run synthesis after all the connections are made and it passes correctly. The issue is when I run implementation I get the error as I have shown in my previous comment. Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?

Hello, could you tell me how do you fix the problem?

What problem? About "Are you saying I have to package the whole design (including the Zync IP, APB bridge, nvdla wrapper, etc) and then run synthesis and implementation?" ? Yes

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[sunny-yellow]

大神，对你的nvdla研究工作很感兴趣，想复现作为自己论文的一部分

[VVViy]

大神，对你的nvdla研究工作很感兴趣，想复现作为自己论文的一部分

欢迎参考，不过我做的这个版本比较久了，官网后续发布的新版本代码可能在工程实现上会有变化，需要你自己摸索了，祝好运~