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VVViy / VVViy.github.io

This is Max's blog, something interesting in it.
MIT License
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create the NVDLA IP for the nv_small with Vivado and manage the connections with the Zynq UltraScale #9

Open ghost opened 5 years ago

ghost commented 5 years ago

did you try to create the NVDLA IP for the nv_small with Vivado? If so, how did you manage the connections with the Zynq UltraScale+?

VVViy commented 5 years ago

Yeah, i did it and have done. In terms of "how", if you know chinese，you can refer to my blog in this repo nv_small FPGA Mapping Workflow .

VVViy commented 5 years ago

Yeah, i did it and have done. In terms of "how", if you know chinese，you can refer to my blog in this repo nv_small FPGA Mapping Workflow .

honorpeter commented 5 years ago

Thank you very much. I will try it as your suggested.

VVViy commented 5 years ago

It's cool, good luck.

ghost commented 5 years ago

I am running nvdla_small spec on Xiliinx Ultrascale Board ZCU102 But,There's a problem : NVDLA a0000000.nvdla_small: failed to register drm device。 cat /proc/interrupts is also not right。 Why,how to solve it? who have the same problem?