Vanillnya / ohdl

Oxidized Hardware Description Language
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Explicit entity signal naming? #9

Open DasLixou opened 5 months ago

DasLixou commented 5 months ago

Having an arch over an entity

entity MyEntity {
    in a: std::Logical,
}

arch RTL for MyEntity {
    AnotherComp {
        a <= a, // this is the important line
    }
}

we currently can directly name the port a from the entity. But since it's not directly in the arch, we may consider to refer to it via self.a (a more rusty approach) or entity.a (my favorite)