Open brinlyau opened 3 years ago
LDAPUR and STLUR were added when Vector35/arch-arm64#101 was closed recently.
reran the script today, updated the OP
Converted the list to checkboxes so we can better track progress. Thanks for maintaining this! Hoping to make some progress on it now.
Thanks! I'm gonna update the table and include the version number each time I update this to make this easier to track.
Aww, then we can't see our progress. 😉 Yeah, that's totally fine. I do think even the current list we've gotten some on dev already which is why I converted with checkboxes. Just re-running and including the version is fine too and we can just ping you when to re-run it.
Including the iPhone13,3_14.1_18A8395 kernelcache here - decompressed
Aww, then we can't see our progress. 😉 Yeah, that's totally fine. I do think even the current list we've gotten some on dev already which is why I converted with checkboxes. Just re-running and including the version is fine too and we can just ping you when to re-run it.
fair enough, that saves me effort haha :)
Ok, as of b3b4ef25a30452f7f35d9c3f2c9c3fb0030eb89e, this is the current status of the instructions mentioned in this issue:
Some SIMD&FP instructions are a hybrid of intrinsics for vector variants and direct lifting for scalar variants.
System instructions and cache control or memory barrier instructions will remain unimplemented for now (but we could make up intrinsics for them, such as we have for rev
and some others).
Load/Store instructions with specific acquire/release or other memory semantics are currently lifted as memory operations, but without any representation of the memory semantics. These could be represented similarly to the ILInstructionAttribute::SrcInstructionUsesPointerAuth
attribute.
The LDn*
and STn*
instructions load and store structures from multiple vector registers, and would require some modifications to the intrinsic code generator.
x
: already done
-
: done in a stash
n
: will not lift
/
: can't figure out
i
: intrinsic
[ ] [n]
at
: Address Translate (will not lift)
[x] b.al
[x] casp
[x] caspal
[x] dup
[x] [i]
fabd
[x] fabs
[x] faddp
[x] fccmp
[x] [i]
fcmeq
[x] [i]
fcmge
[x] [i]
fcmgt
[x] [i]
fcvtl
[x] [i]
fcvtn
[x] [i]
fcvtzs
[x] [i]
fcvtzu
[x] fdiv
[x] fmax
[x] [i]
fmaxnm
[x] [i]
fmin
[x] [i]
fminnm
[x] [i]
fmla
[x] [i]
fmls
[x] fneg
[x] fnmul
[x] hint
[ ] [n]
ic
: Instruction Cache operation.
[ ] ld1r
[ ] ld2
[ ] ld2r
[ ] ld4
[ ] ldclr
[ ] ldclral
[ ] ldclralh
[ ] ldclrb
[ ] ldclrh
[ ] ldclrl
[ ] ldeor
[ ] ldeorb
[ ] ldeorh
[x] [i]
ldlar
[ ] ldset
[ ] ldsetal
[ ] ldsetalb
[ ] ldsetalh
[ ] ldsetb
[ ] ldseth
[ ] ldsetl
[ ] ldsetlh
[ ] ldumax
[ ] ldumaxb
[ ] [n]
mova
: Not currently lifting SME instructions (no intrinsics available)
[x] ngc
[x] ngcs
[x] [i]
raddhn
[x] [i]
rshrn
[ ] [n]
sb
: "Speculation Barrier"
[x] scvtf
[x] smov
[ ] [n]
st1w
: Not currently lifting SVE instructions
[ ] st2
[ ] st4
[x] sxtl
[x] sxtl2
[ ] [n]
sys
: system instruction
[ ] [n]
sysl
: system instruction
[x] [i]
tbl
(also tbx
)
[ ] [n]
tlbi
: TLB Invalidate operation (will not lift)
[x] [i]
uaddl
[x] ucvtf
[x] [i]
umull2
I updated the checklists above, and those changes are merged to dev with c3040ecfc43983af6f05da13cf2242d085b1e230, and should be reflected in builds >= 4.1.5669-dev.
I've made a best effort to lift all the instructions listed here that can be lifted, either directly or via intrinsics, with the possible exception of the ldset
and other ld*
atomic instructions.
(Note also that ld2
& st2
were already lifted to intrinsics, but I haven't really looked at them. All the (ld|st)[1-4]
instructions could probably be handled the same way I handled tbl
.)
Continuing to leave this issue open to track the remaining instructions listed.
I'm aware that this is very much of a stretch-goal that I don't actually expect this to be fully done (and some are SVE ones so we don't have a good way to lift this), but I'm gonna post my list, so people have a better idea about what's missing in a typical iOS kernelcache.
I'll keep updating this list over time - so just see the edited comments (iPhone13,3_14.1_18A8395).
This list may be similar for the dyld_shared_cache and other binaries compiled by Apple's clang. Similar idea to issue Vector35/binaryninja-api#4002 but this is for instructions present in kernels as opposed to usermode code - some crossover may exist.