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VeriSilicon / TIM-VX

VeriSilicon Tensor Interface Module
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Sota pose net needing! #317

Closed 2050airobert closed 1 year ago

2050airobert commented 2 years ago

hi, 1 Any plan of the lite-hrnet coverting to vim3 a311d NPU? 2 How about the sota of pose model just like tinypose ? Could we covert tinypose to the vim3 NPU?

Tks

sunshinemyson commented 2 years ago

if you have tflite model, you don't have to convert it. We have a vx-delegate for tflite can handle this.

2050airobert commented 2 years ago

Any restrict requirement of the tflite？ For example， I will translate the third party model to onnx model, then convert the onnx model to the tensorflow model , then convert the tf model to the tflite model. Any lose or inaccuracy occurs in this coverting process？ And most of all， we can handle this tflite mode also?

sunshinemyson commented 2 years ago

@2050airobert ，

We support standard tflite - if cpu_reference can get it pass, then it should work with our vx-delegate, if any operation is not mapped to our NPU yet, we will fallback it to cpu. You can report the fallback to us, then we can add support for it.

I cannot comment on the conversion procedure, but I think you can find tools fully open sourced from github then give a try.

Thanks

2050airobert commented 2 years ago

Tks, could you share any webchat group like other company which make us communicate conveniently？ As we are working on the a311d ，we want to share or know more similar problem with the TIM-VX framework on the chip. Looking forward to your reply!

sunshinemyson commented 2 years ago

@2050airobert ,

we don't have it right now. It will take some time because company policy. Before that, you can email to our support email.

ML_Support@verisilicon.com