VeriSilicon / TIM-VX

VeriSilicon Tensor Interface Module
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Refine prelu layout inference #577

Closed chenfeiyue-cfy closed 1 year ago

chenfeiyue-cfy commented 1 year ago

In the past we reverse all inputs to default order pv and caused unnecessary transpose operation. In this commit only const input will be transposed if necessary.

Type: Code Improvement