Remove confusing comment in depthwise conv test

VeriSilicon / TIM-VX

VeriSilicon Tensor Interface Module

Other

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Remove confusing comment in depthwise conv test #621

Closed chenfeiyue-cfy closed 1 year ago

chenfeiyue-cfy commented 1 year ago

Remove wrong layout comment for depthwise conv unit test Add comment of layout condition in basic class for depthwise conv Refine above coding style by clang-format

Type: Code Improvement