Closed d1duarte closed 8 years ago
In the reg_256x32b_3r_1w_fpga.v the "web" port in all three banks is assigned with "4'd0" where the port input is only 1bit wide. The value should be changed to "1'd0". This bug prevents Vivado Simulator from opening.
In the reg_256x32b_3r_1w_fpga.v the "web" port in all three banks is assigned with "4'd0" where the port input is only 1bit wide. The value should be changed to "1'd0". This bug prevents Vivado Simulator from opening.