DAY 1 THEORY AND LAB

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Introduction to QFN - 48 package, chip, pads, core, die and IPs

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Introduction to RISC V

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From Software Applications to Hardware

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Introduction to Components of Opensource Digital ASIC Design

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Simplified RTL to GDS flow

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Introduction to OpenLANE and Strive Chipsets

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Introduction to OpenLANE detailed ASIC Design Flow

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Design Preparation Step

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Review Files After Design Prep and Run Synthesis

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Steps to Characterise Synthesis Results