Device Descriptor Request Failed

[Long-Tam]

Hi Wang.

Thanks for sharing your project. I tried to implement your project for an Altera Cyclone II and successfully compile the code after doing a minor adjustment to the PLL so that it works for the Cyclone II board. The rest is left untouched. After uploading the code to the device and plug it in my computer, which runs on Windows 10, it reports Device Descriptor Request Failed: I manage to hook it up to a digital analyser and seeing there is some transactions. I compare the packages of the FPGA implemented your code with that of the pin D+ and D- of a USB UART CP2102 and there seems to be a difference in the control transaction:

This is the control transaction of your the FPGA implemented with your code, it doesn't do handshake after the Data0

And this is the control transaction of a USB UART which end by an ACK handshake

I couldn't figure out any way to resolve this issue. Any help would be appreciated, thanks in advance.

P/s:

• I have checked that the PLL does return a 60MHz clock, which mean that the problem isn't due to the clock.
• And the device do return NAK handshake when the host send an IN token before the SETUP occur, which means that there are communication back and forth.
  

[mauriliomauri]

It seems that the setup is at the address 0x00. This is the default address at the power on and it is ok that the device doesn't respond. Whereas the PID IN is at the address 0x02. You should check the packets after the device accepts its new address with set_address request.

[Long-Tam]

Thanks mauriliomauri, I have just rechecked my connection and it turns out that my FPGA pins' logic high voltage is 5V, after convert it to 3.3 V, everything works.